Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.5 ATU Queue ArchitectureATU operation and performance depends on the queueing mechanism implemented between theinternal bus interface and PCI bus interface. As indicated in Figure 5-2, the ATU queue architectureconsists of separate inbound and outbound queues for ATU. The function of each queue isdescribed in the following sections.5.5.1 Inbound QueuesThe inbound data queues of the ATUs support transactions initiated on a PCI bus and targeted ateither Intel ® 80312 I/O companion chip local memory or a Intel ® 80312 I/O companion chipmemory mapped register. Table 5-4 details the name and sizes of the PATU and SATU inbounddata queues.Table 5-4.Inbound QueuesATU Queue Mnemonic Queue Name Queue Size (Bytes)P_IWQ Primary Inbound Write Data Queue 256P_IWQAD Primary Inbound Write Address Queue 4 Transaction AddressesPATUSATUP_IRQ Primary Inbound Read Data Queue 256P_IDWQ Primary Inbound Delayed Write Queue 8P_ITQ1 Primary Inbound Transaction Queue 1 Address/CommandP_ITQ2 Primary Inbound Transaction Queue 2 Address/CommandS_IWQ Secondary Inbound Write Data Queue 256S_IWQAD Secondary Inbound Write Address Queue 4 Transaction AddressesS_IRQ Secondary Inbound Read Data Queue 256S_ITQ1 Secondary Inbound Transaction Queue 1 Address/CommandS_ITQ2 Secondary Inbound Transaction Queue 2 Address/Command5-32 Developer’s Manual