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Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

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<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>Messaging Unit6.8.17 Outbound Post Head Pointer Register - OPHPRThe Outbound Post Head Pointer Register (OPHPR) contains the local memory offset from theQueue Base Address of the head pointer for the Outbound Post Queue. The Head Pointer must bealigned on a word address boundary. When read, the Queue Base Address is provided in the upper12 bits of the register. Writes to the upper 12 bits of the register are ignored.Table 6-23.Outbound Post Head Pointer Register - OPHPR3128 24 20 16 12 8 4 0PCI IOPAttributes Attributesrororororororororororororororororororororororororw rw rwrw rw rwrw rwrw rwrw rw rw rw rw rw rwrw rw rw rw rw rw rwrwrwrw rw rw rw rwrw rw rw rw rwrvrvrvrvOPHPR<strong>Intel</strong> ® 80200 Processor Local Bus Address1378HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:20 000H Queue Base Address - Local memory address of the circular queues.Outbound Post Head Pointer - Local memory offset of the head pointer for the19:02 0000H 00 2 Outbound Post Queue.01:00 00 2 Reserved6-34 Developer’s Manual

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