Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitWhen an abort (see Section 4.9.1) occurs, either while locked or while attempting to lock, or thediscard timer associated with a locked transaction expires, the bridge will transition to theUnlocking state. When this occurs due to an abort, any remaining enqueued requests are forwardedas unlocked transactions. This ensures that the bridge makes every attempt to pass the lost lockstatus back to the initiating master before accepting more transactions.Downstream lock transactions must begin with a delayed read request (DRR) from the lock master.When a PCI master tries to establish a lock with a write transaction using any PCI write command,the Primary interface accepts the write transaction as an unlocked transaction and forwards it to theSecondary interface without asserting S_LOCK#.Systems which implement multiple Intel ® 80312 I/O companion chips must be aware that there aresituations which can cause lockup conditions when downstream masters are allowed to generatelocked transactions. These lockup conditions can arise due to interactions between the PCItransaction ordering rules and the requirement to restrict transaction forwarding through the bridgewhile locking or locked. This should not present a problem as the only master which typicallygenerates locked transactions is the system host, located on the uppermost PCI bus.Several other precautions are worth noting for systems that forward transactions to downstreamtargets. Since the PCI specification requires that the lock resource be released when the lockedmaster transaction aborts, situations may arise in which the bridge loses its lock on the Secondarybus before the initial locked master is ready to release its lock. The system designer must ensurethat the bridge is configured to allow error or abort status to be reflected upstream to handle thesesituations, otherwise data integrity may be compromised in the shared resource.Finally, since the bridge is required to transition through the Unlocking state before returning toUnlocked, the bridge must be able to empty all of its transaction queues. Discard timers shouldnever be disabled, since timing out may be the only means of emptying the bridge in the event amaster is unable to complete an enqueued transaction.4.9.1 Secondary Interface Error HandlingThe PCI Local Bus Specification, Revision 2.2 states that a master which has lost its bus lock, mustdeassert LOCK#. An issue arises because the specification also states that a master must retry (withLOCK#) all locked outstanding transactions already attempted on the bus.The Secondary interface of the bridge will use the following rules when an abort condition (masteror target) is encountered from a target on the Secondary interface:• Deassert S_LOCK# as masters are required to do when an abort condition is encountered.• Put the bridge into the Unlocked state (see Table 4-19).• Convert all remaining requests within the bridge into non-locked transactions and let themcomplete (locked completions will complete as locked). This includes any outstanding delayedrequests.The converted transactions (on the Secondary interface) may be accepted as new transactions byany downstream bridges. The original master on the initiating bus will release P_LOCK# when theabort condition is reported. This may leave delayed locked requests within downstream bridgequeues which can only be removed by the action of the Discard Timers. In the case of posted writetransactions, it is up to software to use P_SERR# to determine that the transaction aborted on thetarget interface.4-62 Developer’s Manual