Intel 80312 I/O Companion Chip - ECEE

General Purpose Input Output (GPIO) 13This chapter describes the Intel ® 80312 I/O companion chip General Purpose Input Output (GPIO)Unit.13.1 General Purpose Input Output SupportEight pins are provided as General Purpose Input Output (GPIO) pins. The eight pins areGPIO[7:0]. These pins can be used by the Intel ® 80200 processor based on Intel ® XScale microarchitecture (ARM* architecture compliant) to control or monitor external devices in the I/Osubsystem.13.1.1 General Purpose InputsThe current state of the eight GPIO pins can be read in Section 13.2.2, “GPIO Input Data Register -GPID”onpage13-4).13.1.2 General Purpose OutputsThe output function of the GPIO pins is controlled by two registers, as stated in Section 13.2.3,“GPIO Output Data Register - GPOD” on page 13-5) andSection 13.2.1, “GPIO Output EnableRegister - GPOE” on page 13-2).The output enables are mapped on a per bit basis to each of the data bits in the GPIO Output DataRegister. When a bit of the GPIO Output Enable Register is cleared, the corresponding data bitvalue in the GPIO Output Data Register is actively driven on the appropriate GPIO pin.13.1.3 Reset Initialization of General Purpose Input OutputFunctionBoth the GPIO Output Data Register and the GPIO Input Data Register is initialized to 00H uponassertion of P_RST#.The GPIO Output Enable Register is initialized to the value of the eight associated GPIO pins uponassertion of P_RST#. The I/O pin design provides internal weak pull-up devices that are driven onthe GPIO pin during P_RST# assertion.In order to enable a particular GPIO pin to operate as an output following the deassertion ofP_RST#, the user needs to provide a weak pull-down on the GPIO pin, to overdrive the internalweak pull-up device.Developer’s Manual 13-1