Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.2.2 Delayed TransactionsDelayed transactions are a method for processing PCI transactions that may exceed the PCI LocalBus Specification, Revision 2.2 requirement for no more than 16 clocks of latency between the PCIaddress and the first data word.The bridge will process all transactions as Delayed transactions, except for Memory Write andMemory Write and Invalidate transactions. These two transactions can be processed as Postedtransactions or as delayed write transactions. When the Posting Disable bit in the Extended BridgeControl Register is clear, Memory Write and Memory Write and Invalidate transactions will beprocessed as Posted transactions (default state). When Posting Disable bit is set, Memory Writecommands will be processed as Delayed transactions and Memory Write and Invalidate commandswill be processed as delayed Memory Write commands.In a Delayed transactions performed by the bridge, the address, command, REQ64# and byteenable information required to complete the transaction is latched by the bridge in a transactionqueue and the initiator is signaled a retry. For writes, the information includes the data to be writtenas well. The bridge performs the request on the target bus on behalf of the initiator. For reads, thereturned data and the target response is stored in the bridge delayed read completion (DRC)queues. For writes, only the target response is recorded. The retried initiator must then repeat theoriginal request on the initiating bus in order complete the full transaction.A Delayed transaction consists of three parts:• Request phase on the initiating bus• Completion phase on the target bus• Completion phase on the initiating busThe request phase is when the transaction information is latched by the bridge and the bridgeterminates the transaction with a Retry. This is referred to as a Delayed Request phase.Once a Delayed Request transaction is accepted by the bridge, the bridge will initiate a completionphase on the target bus using the same transaction type as on the initiating bus. Data thataccompanies the request transactions for delayed writes is held in the bridge delayed write request(DWR) queues. Data being returned for reads is written into the DRC queues.The completion phase on the initiating bus is when the initiator repeats the original request and thebridge signals a termination other than Retry. This is referred to as a Delayed Completiontransaction. The Delayed Completion transaction will terminate with the same termination as thetarget bus transaction. For example, when the target bus transaction terminated with Disconnect,the Delayed Completion transaction will terminate with Disconnect.The bridge has a discard timer associated with each data buffer used for Delayed transactions (seeSection 4.11.4). When the discard timer expires before the initiator repeats the original request, thedata and associated request information is discarded.4-30 Developer’s Manual