Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipApplication Accelerator UnitWhen multiple chain descriptors are built in Intel ® 80200 processor local memory, the applicationcanlinkeachofthesechaindescriptorsusingtheNextDescriptorAddressinthechaindescriptor.This address logically links the chain descriptors together. This allows the application to build a listof transfers which may not require the use of the Intel ® 80200 processor until all transfers arecomplete. Figure 10-4 shows an example of a linked-list of transfers specified in external memory.Figure 10-4.XOR Chaining OperationDescriptor Address RegisterAccelerator Control RegisterLinked Descriptors In Local MemoryNext Descriptor Address (NDA)Source Address (SAR1)Source Address (SAR2)Source Address (SAR3)Source Address (SAR4)Destination Address (DAR)Byte Count (BC)Descriptor Control (DC)Buffer TransfersFirst Chain DescriptorXOROperationNext Descriptor Address (NDA)Source Address (SAR1)Source Address (SAR2)Source Address (SAR3)Source Address (SAR4)Destination Address (DAR)Byte Count (BC)Descriptor Control (DC)Second Chain DescriptorXOROperation...Next Descriptor Address (NDA)Source Address (SAR1)Source Address (SAR2)Source Address (SAR3)Source Address (SAR4)Destination Address (DAR)Byte Count (BC)Descriptor Control (DC)End of Chain(Null Value Detected)Nth Chain DescriptorXOROperation10-6 Developer’s Manual
Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.3.3 Chain Descriptor Format (Eight Source Addresses)To perform an XOR-transfer with more than 4 source blocks of data (up to 8), a special chaindescriptor needs to be configured:• The first part (principal-descriptor) contains the address of the first 4 source data blocks alongwith other information.• The second part (mini-descriptor) contains 4, 32-bit words containing the address of theadditional four (SAR5 - SAR8) source data blocks. The mini-descriptor is written to acontiguous address immediately following the principal descriptor.To perform a transfer, both parts (principal and mini-descriptor) must be written to Intel ® 80200processor local memory. Figure 10-5 shows the format of this configuration. Every descriptorrequires twelve contiguous words in Intel ® 80200 processor local memory and is required to bealigned on an 8-word boundary. All twelve words are required.Figure 10-5.Chain Descriptor Format for Eight Source Addresses (XOR Function)Chain Descriptor in Intel ® 80200Next Descriptor Address (NDA)Source Address (SAR1)Source Address (SAR2)Source Address (SAR3)Source Address (SAR4)Destination Address (DAR)Byte Count (BC)Descriptor Control (DC)Source Address (SAR5)Source Address (SAR6)Source Address (SAR7)Source Address (SAR8)DescriptionAddress of Next Chain DescriptorSource Address for first block of dataSource Address for second block of dataSource Address for third block of dataSource Address for fourth block of dataDestination Address of XOR-ed dataNumber of bytes to XORDescriptor ControlSource Address for fifth data blockSource Address for sixth data blockSource Address for seventh data blockSource Address for eighth data block• The first word is the Intel ® 80200 processor local memory address of the next chain descriptor.A value of zero specifies the end of the chain. This value is loaded into the Accelerator NextDescriptor Address Register. Because chain descriptors must be aligned on an 8-wordboundary, the unit may ignore bits 04:00 of this address.• The second word is the address of the first block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into SAR1.• The third word is the address of the second block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into SAR2.• The fourth word is the address of the third block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into SAR3.• The fifth word is the address of the fourth block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into SAR4.Developer’s Manual 10-7
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Intel 80312 I/O Companion Chip - ECEE

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