Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-55. Secondary Decode Enable Register - SDER (Sheet 2 of 2)IOPAttributes15 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rvPCIAttributesrw rw rw rw rw rw rw rw rw rw rw rw rw rw rwrvPCI Configuration Offset5C - 5DHIntel ® 80200 Processor Local Bus Address0000 105CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description09 1 2Primary PCI Master Abort Interrupt Mask - When set, a master abort error resulting in bit 13 of the PSRbeing set will not result in bit 3 of the PBISR being set. When clear, an error that sets bit 13 of the PSRwillcausebit3ofthePBISRtobeset.08 1 2Primary PCI Target Abort (Master) Interrupt Mask- When set, a target abort error resulting in bit 12 of thePSR being set will not result in bit 2 of the PBISR being set. When clear, an error that sets bit 12 of thePSR will cause bit 2 of the PBISR to be set.07 1 2Primary PCI Target Abort (Target) Interrupt Mask - When set, a target abort error resulting in bit 11 of thePSR being set will not result in bit 1 of the PBISR being set. When clear, an error that sets bit 11 of thePSR will cause bit 1 of the PBISR to be set.06 1 2Primary PCI Master Parity Error Interrupt Mask - When set a parity error resulting in bit 8 of the PSRbeing set will not result in bit 0 of the PBISR being set. When clear, an error that sets bit 8 of the PSR willcausebit0ofthePBISRtobeset.Secondary Detected Parity Error Bit Interrupt Mask - When set a parity error resulting in bit 15 of the05 1 2 SSR being set will not result in bit 5 of the SBISR being set.Primary Detected Parity Error Bit Interrupt Mask - When set a parity error resulting in bit 15 of the PSR04 1 2 being set will not result in bit 5 of the PBISR being set.03 1 2 deassertion (by software only) of bit 6, Secondary Bus Reset, in the BCR, bit 6 of the SBISR will not beSecondary Bus Reset Occurred Interrupt Mask - When this bit is set, and the bridge senses theset.02 0 2Private Memory Space Enable - when set, this bit disables Bridge forwarding of addresses in theSMBR/SMLR and SIOBR/SIOLR address ranges. This creates a private memory space on theSecondary PCI bus that allows peer to peer transactions.01 1 2Power State Transition Interrupt Mask - When this bit is set and the Power Management Control/StatusRegister is written to transition the Bridge Function Power State from either D0 to D3 or D3 to D0, bit 6 ofthe PBISR is not set.00 0 2 Reserved.4-122 Developer’s Manual