Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipClocking, Reset, and Initialization15.2 Reset OverviewThere are three ways to reset the Intel ® 80312 I/O companion chip. The main reset is controlledthrough the primary PCI bus reset signal (P_RST#). When the primary PCI bus asserts this signal,the entire Intel ® 80312 I/O companion chip is placed in a reset state. In addition to the primary PCIreset pin, the Intel ® 80312 I/O companion chip provides software control of units within the Intel ®80312 I/O companion chip and the secondary PCI interface.Figure 15-3 shows the logical block diagram of the reset conditions.Figure 15-3.Reset Block DiagramPrimaryPCI BusPrimaryRST#DMAChannelsAddressTranslationUnitMemoryControllerPCI to PCIBridge UnitPerformanceMonitorUnitSecondary Bus Reset bit OR P_RST#SecondaryRST#Internal Bus Reset bit OR P_RST#AddressTranslationUnitDMAChannelSecondaryPCIArbiterInternal BusLocal BusArbitrationUnitApplicationAcceleratorUnitI2CInterfaceUnitInternalBus ResetI_RST#SecondaryPCI Bus6Req/GntPairsWhen the primary PCI signal (P_RST#) is asserted, the reset signal causes all configurationregisters, internal control and enable signals, state machines, and output buffers to their initializedstate. For any signal attached to the PCI bus, the specification is well defined.Developer’s Manual 15-5