Intel 80312 I/O Companion Chip - ECEE

DMA Controller Unit 9This chapter describes the integrated Direct Memory Access (DMA) Controller Unit. Theoperation modes, setup, external interface, and implementation of the DMA Controller are detailedin this chapter.9.1 OverviewThe DMA Controller provides low-latency, high-throughput data transfer capability. The DMAController optimizes block transfers of data between the PCI bus and the Intel ® 80200 processorbasedonIntel ® XScale microarchitecture (ARM architecture compliant) local memory. TheDMA is an initiator on the PCI bus with burst capabilities providing a maximum throughput of528 Mbytes/sec when the PCI bus is operating in 64-bit/66 MHz mode.The DMA Controller hardware is responsible for executing data transfers and for providing theprogramming interface. The DMA Controller features:• Three Independent Channels• 256-byte queues in Ch-0 and Ch-1• 64-byte queue in Ch-2• Utilization of the Intel ® 80312 I/O companion chip Memory Controller Interface• 2 32 addressing range on the Internal Bus interface• 2 64 addressing range on the primary and secondary PCI interfaces by using PCI Dual AddressCycle (DAC)• Independent PCI interfaces to the primary and secondary PCI buses• Hardware support for unaligned data transfers for both the PCI bus and the Internal Bus• Up to 528 Mbytes/sec burst support for the PCI bus• Up to 800 Mbytes/sec burst support for the Intel ® 80312 I/O companion chip internal bus• Direct addressing to and from the PCI bus• Fully programmable directly from the Intel ® 80200 processor• Support for automatic data chaining for gathering and scattering of data blocks• 64-bit/66 MHz PCI• 64-bit/100 MHz Intel ® 80312 I/O companion chip Internal Bus interface.Developer’s Manual 9-1