Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface UnitTable 12-10. I 2 C Status Register - ISR (Sheet 2 of 2)IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rc rc rc rc rc ro ro ro roPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Local Bus Address1684HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07 0 20 = The IDBR has not received a new data byte or the I 2 C unit is idle.1 = The IDBR register received a new data byte from the I 2 C bus. An interrupt is signalled whenIDBR Receive Full:enabled in the ICR.06 0 20= Thedatabyteisstillbeingtransmitted.1= TheI 2 C unit has finished transmitting a data byte on the I 2 C bus. An interrupt is signalled whenIDBR Transmit Empty:enabled in the ICR.05 0 2 0 = Cleared when arbitration is won or never took place.Arbitration Loss Detected: used during multi-master operation.1 = Set when the I 2 C unit loses arbitration.04 0 2 0= NoSTOPdetected.Slave STOP Detected:1 = Set when the I 2 C unit detects a STOP while in slave-receive or slave-transmit mode.03 0 20= I 2 C bus is idle or the I 2 C unit is using the bus (i.e., unit busy).1 = Set when the I 2 C bus is busy but the Intel ® 80312 I/O companion chip’s I 2 C unit is not involved inI 2 CBusBusy:the transaction.02 0 20= I 2 C unit not busy.1 = Set when the Intel ® 80312 I/O companion chip’s I 2 C unit is busy. This is defined as the timeUnit Busy:between the first START and STOP.01 0 2Ack/Nack Status:0= TheI 2 C unit received or sent an Ack on the bus.1= TheI 2 C unit received or sent a Nack.This bit is used in slave transmit mode to determine when the byte transferred is the last one. This bit isupdated after each byte and Ack/Nack information is received.00 0 20= TheI 2 C unit is in master-transmit or slave-receive mode.1= TheI 2 C unit is in master-receive or slave-transmit mode.Read/Write Mode:This is the R/W# bit of the slave address. It is automatically cleared by hardware after a stop state.Developer’s Manual 12-31