Intel 80312 I/O Companion Chip - ECEE

More documents

Recommendations

Info

Intel ® 80312 I/O Companion ChipMemory Controller3.2.2.3 Flash Write CycleAddress-to-data and recovery wait states for reads and writes are identical and programmed inFWSR0 and FWSR1. Refer to Table 3-4 for the programmable address-to data wait states.The MCU claims internal bus transactions and accepts the data with zero wait-states, thus freeingthe internal bus. However, the MCU remains busy until the cycle completes on the Flash interface.Subsequent MCU cycles are retried on the internal bus during this period.The MCU does not support bursting data to a Flash device since the Flash device has no writebuffers to support bursting data.Figure 3-5 illustrates a write cycle to a 90 ns Flash device.Figure 3-5.90 ns Flash Write CycleT AT A T A T 1 T 2 T 3 T 41316 17T 5 T 6 T 7 T 8 T D T R T R T RT RDCLK0 1 2 3 4 5 6 7 8 9 10 11121415RCE#ROE#RWE#AD[2:0]ADDR[2:0]AD[8:3]AD[16:9]RALEADDR[22:17]ADDR[16:9]ADDR[8:3]D 0Address14-bit External LatchDecode3-10 Developer’s Manual
Intel ® 80312 I/O Companion ChipMemory Controller3.2.3 SDRAM Memory SupportThe Intel ® 80312 I/O companion chip memory controller supports one or two banks of SDRAM.SDRAM allows zero data-to-data wait-state operation at 100 MHz. SDRAM offers an extremelywide range of configuration options emerging from the SDRAMs internal interleaving and burstingcapabilities.The MCU supports SDRAM burst lengths of four. A burst length of four enables seamlessread/write bursting of long data streams as long as the MCU master does not cross the pageboundary. Page boundaries are at naturally aligned 2 Kbyte blocks for the 64-bit data bus. TheMCU ensures that the page boundary is not crossed within a single transaction by initiating adisconnect with data on the Internal Bus prior to the page boundary.The MCU SDRAM interface provides a flexible mix of combinations including:Table 3-5 shows the SDRAM interface signals.Table 3-5.SDRAM Interface SignalsPin NameDCLK[3:0]DCLKOUTDCLKINSCKE[1:0]SDQM[7:0]SCE[1:0]#SWE#SBA[1:0]SA[10]DescriptionSDRAM Output Clocks - These are the four output clocks driven to the Unbuffered DIMMssupported by the Intel ® 80312 I/O companion chip. Section 3.2.6, “SDRAM Clocking” onpage 3-34 describes the SDRAM clocking strategy.SDRAM Feedback clock - This clock is driven in to the memory subsystem so thatDCLK[3:0] may be skewed back to accommodate for the clocks’ flight time and becompatible with 100/133 MHz SDRAM technologiesSDRAM Clock In -ThisistheDCLKOUT clock returning from the memory subsystem.Section 3.2.6, “SDRAM Clocking” on page 3-34 describes the SDRAM clocking strategy.Clock enables - One clock after SCKE[1:0] is deasserted, the data is latched on DQ[63:0]and SCB[7:0]. The burst counters within the SDRAM device are not incremented.Deasserting this signal places the SDRAM in self-refresh mode. For normal operation,SCKE[1:0] must be asserted.Data Mask - On a write, these signals enable the eight output data bytes required by the64-bit data bus. On a read, two clocks after asserting SDQM[7:0] the output data bytes aredisabled.Chip Select - Must be asserted for all transactions to the SDRAM device. One per bank.Write Enable - Controls the SDRAM data input buffers. Asserting SWE# causes the data onDQ[63:0] and SCB[7:0] to be written into the SDRAM devices.SDRAM Bank Selects - Controls which of the internal SDRAM banks to read or write. For16 Mbit devices (2 banks), only SBA[0] is used while 64 Mbit devices use SBA[1:0].Address bit 10 - When high during a read or write command, auto-precharge occurs afterthe command. During a row-activate command, this bit is part of the address (seeTable 3-6).SA[12:0]Address bits 12 through 0 - Indicates the row or column to access depending on the state ofSRAS# and SCAS# (see Table 3-10).SA[13] Address bit 13 - Enables the use of 16Mx16 memory devices. (see Table 3-11)SRAS# Row Address Strobe - Indicates that the current address on SA[12:0] is the row.SCAS# Column Address Strobe - Indicates that the current address on SA[12:0] is the column.DQ[63:0] Data Bus - 64-bit wide data bus.SCB[7:0] ECC Bus - 8-bit error correction code which accompanies the data on DQ[63:0].Utilizing the SDRAM chip enables SCE[1:0]# and internal bank selects SBA[1:0],theMCUkeepsa maximum of eight pages open simultaneously with 64/128/256 Mbit devices. The number ofavailable pages depends on the memory subsystem population. A single 64/128/256 Mbit SDRAMbank allows four pages and two banks allow eight pages.Developer’s Manual 3-11
Page 1 and 2:
Intel ® 80312 I/O Companion ChipDe
Page 3 and 4:
Intel ® 80312 I/O Companion ChipCo
Page 5 and 6:
Intel ® 80312 I/O Companion Chip3.
Page 7 and 8:
Intel ® 80312 I/O Companion Chip4.
Page 9 and 10: Intel ® 80312 I/O Companion Chip5.
Page 11 and 12: Intel ® 80312 I/O Companion Chip7.
Page 13 and 14: Intel ® 80312 I/O Companion Chip10
Page 18 and 19: Intel ® 80312 I/O Companion ChipFi
Page 22 and 23: Intel ® 80312 I/O Companion Chip4-
Page 24 and 25: Intel ® 80312 I/O Companion Chip5-
Page 28 and 29: Intel ® 80312 I/O Companion ChipIn
Page 35 and 36: PCI and Peripheral Interrupt Contro
Page 37 and 38: Intel ® 80312 I/O Companion ChipPC
Page 51 and 52: Memory Controller 3This chapter des
Page 53 and 54: Intel ® 80312 I/O Companion ChipMe
Page 59: Intel ® 80312 I/O Companion ChipMe
Page 111:
Intel ® 80312 I/O Companion ChipMe
Page 114 and 115:
Intel ® 80312 I/O Companion ChipPC
Page 116 and 117:
Page 118 and 119:
Page 120 and 121:
Page 122 and 123:
Page 124 and 125:
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
.Intel ® 80312 I/O Companion ChipP
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Page 172 and 173:
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Page 188 and 189:
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
Page 196 and 197:
Page 198 and 199:
Page 200 and 201:
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Page 212 and 213:
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
Page 236 and 237:
Page 238 and 239:
Page 240 and 241:
Page 242 and 243:
Page 244 and 245:
Page 246 and 247:
Page 248 and 249:
Page 250 and 251:
Page 252 and 253:
Page 254 and 255:
Page 256 and 257:
Page 258 and 259:
Page 260 and 261:
Page 262 and 263:
Page 264 and 265:
Page 266 and 267:
Page 268 and 269:
Page 270 and 271:
Page 272 and 273:
Page 274 and 275:
Page 276 and 277:
Page 278 and 279:
Page 280 and 281:
Page 282 and 283:
Page 284 and 285:
Page 286 and 287:
Page 288 and 289:
Page 290 and 291:
Page 292 and 293:
Page 294 and 295:
Page 296 and 297:
.Intel ® 80312 I/O Companion ChipP
Page 298 and 299:
Page 300 and 301:
Page 302 and 303:
Page 304 and 305:
Page 306 and 307:
Page 308 and 309:
Page 310 and 311:
Page 312 and 313:
Page 314 and 315:
Page 316 and 317:
Page 318 and 319:
Page 320 and 321:
Page 322 and 323:
Page 324 and 325:
Page 326 and 327:
Page 328 and 329:
Page 330 and 331:
Page 332 and 333:
Page 334 and 335:
Page 336 and 337:
Page 338 and 339:
Page 340 and 341:
Page 342 and 343:
Page 344 and 345:
Page 346 and 347:
Page 348 and 349:
Page 350 and 351:
Page 352 and 353:
Page 354 and 355:
Page 357 and 358:
Messaging Unit 6This chapter descri
Page 359 and 360:
Page 361 and 362:
Page 363 and 364:
Page 365 and 366:
Page 367 and 368:
Page 369 and 370:
Page 371 and 372:
Page 373 and 374:
Page 375 and 376:
Page 377 and 378:
Page 379 and 380:
Page 381 and 382:
Page 383 and 384:
Page 385 and 386:
Page 387 and 388:
Page 389 and 390:
Page 391 and 392:
Page 393 and 394:
Intel ® 80312 I/O Companion ChipAr
Page 395 and 396:
Intel ® 80312 I/O Companion ChipIn
Page 397 and 398:
Page 399 and 400:
Page 401 and 402:
Page 403 and 404:
Page 405 and 406:
Page 407 and 408:
Page 409 and 410:
Intel ® 80200 Processor based on I
Page 411 and 412:
Page 413 and 414:
Page 415 and 416:
Page 417 and 418:
Page 419 and 420:
Page 421 and 422:
Page 423 and 424:
DMA Controller Unit 9This chapter d
Page 425 and 426:
Intel ® 80312 I/O Companion ChipDM
Page 427 and 428:
Page 429 and 430:
Page 431 and 432:
Page 433 and 434:
Page 435 and 436:
Page 437 and 438:
Page 439 and 440:
Page 441 and 442:
Page 443 and 444:
Page 445 and 446:
Page 447 and 448:
Page 449 and 450:
Page 451 and 452:
Page 453 and 454:
Page 455 and 456:
Page 457 and 458:
Page 459 and 460:
Application Accelerator Unit 10This
Page 461 and 462:
Intel ® 80312 I/O Companion ChipAp
Page 463 and 464:
Page 465 and 466:
Page 467 and 468:
Page 469 and 470:
Page 471 and 472:
Page 473 and 474:
Page 475 and 476:
Page 477 and 478:
Page 479 and 480:
Page 481 and 482:
Page 483 and 484:
Page 485 and 486:
Page 487 and 488:
Page 489 and 490:
Page 491:
Page 494 and 495:
Intel ® 80312 I/O Companion ChipPe
Page 496 and 497:
Page 498 and 499:
Page 500 and 501:
Page 502 and 503:
Page 504 and 505:
Page 506 and 507:
Page 508 and 509:
Page 510 and 511:
Page 512 and 513:
Page 514 and 515:
Page 516 and 517:
Page 518 and 519:
Page 520 and 521:
Page 522 and 523:
Intel ® 80312 I/O Companion ChipI
Page 524 and 525:
Page 526 and 527:
Page 528 and 529:
Page 530 and 531:
Page 532 and 533:
Page 534 and 535:
Page 536 and 537:
Page 538 and 539:
Page 540 and 541:
Page 542 and 543:
Page 544 and 545:
Page 546 and 547:
Page 548 and 549:
Page 550 and 551:
Page 552 and 553:
Page 554 and 555:
Page 557 and 558:
General Purpose Input Output (GPIO)
Page 559 and 560:
Intel ® 80312 I/O Companion ChipGe
Page 561:
Intel ® 80312 I/O Companion ChipGe
Page 564 and 565:
Intel ® 80312 I/O Companion ChipTe
Page 566 and 567:
Page 568 and 569:
Page 570 and 571:
Page 572 and 573:
Page 574 and 575:
Page 576 and 577:
Page 578 and 579:
Page 580 and 581:
Page 582 and 583:
Page 584 and 585:
Page 586 and 587:
Page 588 and 589:
Page 590 and 591:
Intel ® 80312 I/O Companion ChipCl
Page 592 and 593:
Page 594 and 595:
Page 596 and 597:
Page 598 and 599:
Page 600 and 601:
Page 602 and 603:
Page 604 and 605:
Page 607 and 608:
Peripheral Memory-Mapped Registers
Page 609 and 610:
Page 611 and 612:
Page 613 and 614:
Page 615 and 616:
Page 617 and 618:
show all

Intel 80312 I/O Companion Chip - ECEE

Create successful ePaper yourself

Delete template?

Save as template?