Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.8.13 Inbound Post Head Pointer Register - IPHPRThe Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the QueueBase Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned ona word address boundary. When read, the Queue Base Address is provided in the upper 12 bits ofthe register. Writes to the upper 12 bits of the register are ignored.Table 6-19.Inbound Post Head Pointer Register - IPHPR3128 24 20 16 12 8 4 0PCI IOPAttributes Attributesrororororororororororororororororororororororororw rw rwrw rw rwrw rwrw rwrw rw rw rw rw rw rwrw rw rw rw rw rw rwrwrwrw rw rw rw rwrw rw rw rw rwrvrvrvrvIPHPRIntel ® 80200 Processor Local Bus Address1368HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:20 000H Queue Base Address - Local memory address of the circular queues.Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound19:02 0000H 00 2 Post Queue.01:00 00 2 Reserved6-30 Developer’s Manual