13.07.2015 Views

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

SHOW MORE
SHOW LESS
  • No tags were found...

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>Messaging Unit6.8.10 Queue Base Address Register - QBARThe Queue Base Address Register (QBAR) contains the local memory address of the CircularQueues. The base address must be located on a 1 Mbyte address boundary.All Circular Queue head and tail pointers are based on the QBAR. When the head and tail pointerregisters are read, the Queue Base Address is returned in the upper 12 bits. Writing to the upper 12bits of the head and tail pointer registers does not affect the Queue Base Address or Queue BaseAddress Register.Table 6-16.Queue Base Address Register - QBARPCI IOPAttributes Attributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rvrw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rvQBAR<strong>Intel</strong> ® 80200 Processor Local Bus Address1354HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:20 000H Queue Base Address - Local memory address of the circular queues.19:00 00000H ReservedDeveloper’s Manual 6-27

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!