Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipDMA Controller UnitTable 9-5. Channel Status Register - CSR (Sheet 2 of 2)IOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv ro rc rc rv rc rc rv rc rc rv rccaeoteocmatappePCIAttributesnanananananananananananananananananananananananananananananananaChannel #012Intel ® 80200 Processor Local Bus Address1404H1444H1484HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description01 0 2 ReservedPCI Parity Error Flag - is set when the following conditions are met:00 0 2 • DMA channel asserted PERR# or has observed PERR# asserted• DMA channel was the master for the transaction during which the error occurred9-28 Developer’s Manual
Intel ® 80312 I/O Companion ChipDMA Controller Unit9.14.3 Next Descriptor Address Register - NDARThe Next Descriptor Address Register (NDARx) contains the address of the next chain descriptorin the Intel ® 80200 processor local memory for a DMA transfer. When starting a DMA transfer,this register contains the address of the first chain descriptor. Table 9-6 depicts the Next DescriptorAddress Register.All chain descriptors are required to be aligned on an eight 32-bit word boundary. The channel mayset bits 04:00 to zero when loading this register.Note:Table 9-6.The Channel Enable bit in the CCR and the Channel Active bit in the CSR must both be clear priorto writing the Next Descriptor Address Register. Writing a value to this register while the channelis active may result in undefined behavior.Next Descriptor Address Register - NDARIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rvPCIAttributesnanananananananananananananananananananananananananananananananaChannel #012Intel ® 80200 Processor Local Bus Address1410H1450H1490HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default DescriptionNext Descriptor Address - local memory address of the next chain descriptor to be read by the channel.0000000000031:05 0000000000000000 204:00 00000 2 ReservedDeveloper’s Manual 9-29
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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Intel 80312 I/O Companion Chip - ECEE

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