Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2.3.3 Page Hit/Miss DeterminationThe MCU address translation assumes a 2 Kbyte page even when the physical addressing allows agreater page size. For 64/128/256 Mbit devices, the MCU keeps four pages per bank (8 maximum)open simultaneously.For 64/128/256 Mbit devices, the MCU keeps only one page each of Bank0/Leaf0, Bank0/Leaf1,Bank0/Leaf2, Bank0/Leaf3, Bank1/Leaf0, Bank1/Leaf1, Bank1/Leaf2, and Bank1/Leaf3 opensimultaneously. This rule implies that one 2 Kbyte page per eighth of the memory can be open. SeeFigure 3-8 for an example organization using 64 Mbit devices.Figure 3-7.Page Hit/Miss Logic for 64/256-bit ModeSCE[1:0]#SBA[1:0]Page RegistersBank 0 Leaf 0Bank 0 Leaf 1Valid Open Page Address 0Valid Open Page Address 1Bank 0 Leaf 2Bank 0 Leaf 3Bank 1 Leaf 0Valid Open Page Address 2Valid Open Page Address 3Valid Open Page Address 4I_AD[31:10]Bank 1 Leaf 1Bank 1 Leaf 2Valid Open Page Address 5Valid Open Page Address 6Bank 1 Leaf 3ValidOpen Page Address 7Page RegisterSelectEnablePage ComparatorA8297-01The MCU paging logic determines the hit/miss status for reads and writes. For a new SDRAMtransaction, the MCU compares the address of the current transaction with the address stored in theappropriate page address register. Assuming 64/128/256 Mbit SDRAM devices and two banks,there are eight pages kept open simultaneously. The SDRAM chip enables (SCE[1:0]#) andleafselects (SBA[1:0]) determine which page address to compare.When the current transaction misses the open page selected then the MCU closes the open pagepointedtobySCE[1:0]# and SBA[1:0] by issuing a precharge command. The MCU opens thecurrent page with a row-activate command and the transaction completes with a read or writecommand. When the MCU opens the current page, I_AD[31:11] is stored in the page addressregister pointed to by SCE[1:0]# and SBA[1:0] so it may be compared for future transactions.When the current transaction hits the open page, then the page is already active and the read orwrite command may be issued without a row-activate command. When the refresh timer expiresand the MCU issues an auto-refresh command, all pages are closed.Figure 3-11 illustrates the performance benefit of a read hit versus a read miss in Figure 3-12.Figure 3-13 illustrates the performance benefit of a write hit versus a write miss in Figure 3-14.3-16 Developer’s Manual