Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.5.1.1 Inbound Write Queue StructureThe PATU and SATU Inbound Write Queues consist of the inbound write data queues and theinbound write address queues. The inbound write data queue hold the data for memory writetransactions moving from a PCI Bus to the internal bus and the address queues hold thecorresponding address of the transactions in the data queues. The primary inbound write queue,P_IWQ, has a queue depth of 256 bytes and moves write transactions from the primary PCI bus tothe internal bus. The corresponding address queue, P_IWQAD, is capable of holding 4 addressentries. The queue pair is capable of holding up to 4 memory write (or MWI) transactions up to thesize of the queue in a manner similar to the bridge unit write queues.The secondary inbound write queue (S_IWQ) has a depth of 256 bytes and moves writetransactions from the secondary PCI bus to the internal bus. The corresponding address queue,S_IWQAD, is capable of holding 4 address entries. This queue pair functions the same as theprimary queue pair, holding up to 4 transactions of variable length up to the size of the data queue.Memory write transactions fill the tail of the queue on the PCI bus and are drained from the head ofthe queue on the internal bus. The following rules apply to the PCI bus interface and govern theacceptance of data into the tail of IWQ and address into the tail of the IWQAD:• A memory write operation claimed by the slave PCI interface on the PCI bus is accepted intothe address and data queues when the queues are in a non-full state (see Section 5.7.48,“Primary ATU Queue Control Register - PAQCR” on page 5-112 and Section 5.7.49,“Secondary ATU Queue Control Register - SAQCR” on page 5-113). A Retry is signaledwhen this condition is not true when a transaction is first claimed by the slave interface.• If the IWQ reaches a full state while filling, a disconnect with data is signaled to the master ofthe transaction on the data phase that fills the queue to a completely full state (no queue bytesremaining).Memory write transactions are drained from the head of the queue when the master interface hasacquired bus ownership and transaction ordering and priority have been satisfied (seeSection 5.5.3). A memory write transaction is considered drained from the queue when the entireamount of data entered on the PCI bus has been accepted by the internal bus target. Errorconditions resulting in the cancellation of a write transaction (master-abort) only flush thetransaction at the head of the data and address queue. All other transactions within the queues areconsidered still valid. Memory Write and Invalidate transactions are treated like Memory Writetransactions on the PCI interface and use the Memory Write command on the internal bus.Transactions entering the tail of an empty queue (no previous write transactions reside in queue)are forwarded immediately to the head of the queue. A queue entry (8 bytes for either 64-bit or32-bit data) is immediately added to the tail of the data queue when drained from the head of thequeue on the target bus.Developer’s Manual 5-33