Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80312 I/O Companion Chip ArbitrationIf any of the below three rules are satisfied, the arbiter may deassert one master’s GNT# in order toservice a higher priority master:Rule 1:Rule 2:Rule 3:With GNT# deasserted and FRAME# asserted, the bus transaction is valid and continues.Once a master initiates a transaction by asserting FRAME# because the arbiter has grantedthat master the PCI bus, the arbiter may deassert its GNT# to service the next master.If the bus master asserts FRAME# and the PCI Arbiter removes its grant on the samecycle, the master assumes ownership of the bus and the arbiter behaves as if the bus wasgranted and claimed by the original master.One GNT# can be deasserted coincident with another GNT# being asserted when the busis not in the idle state. Otherwise, a one clock delay is added between the deassertion of aGNT# and the assertion of the next GNT#. This prevents contention on the AD[63:0] bus.An idle state is defined as a cycle where FRAME# and IRDY# are deasserted. If thePCI bus appears to be idle, a master may actually be using “stepping” to drive the PCIbus. Stepping requires the master to drive AD[63:0] one cycle prior to the master’sassertion of FRAME#. Refer to the PCI Local Bus Specification, Revision2.2formoredetails on address/data stepping.The PCI Arbiter always satisfies this rule since the arbiter always asserts a master’sGNT# one cycle after deasserting another master’s GNT#.While FRAME# is deasserted, GNT# may be deasserted any time in order to serviceanother master, or in response to the associated REQ# being deasserted.The PCI Arbiter continually updates the bus owner for the next transaction. Forexample, assume the arbiter grants the next transaction to a device of medium priority(Master_A). If a high priority device (Master_B) requests the PCI bus prior to Master_Aclaiming the bus by asserting FRAME#, the arbiter deasserts Master_A’s GNT# andassert Master_B’s GNT# one clock later.Note:The PCI Arbiter arbitrates the PCI bus by checking REQ[8:0]# on every cycle independentof any transactions on the bus 1 .By monitoring REQ[8:0]#, the arbiter can control the arbitration algorithm described inSection 7.2.1.1, “Priority Mechanism” on page 7-3. The arbiter asserts GNT# two clocks after REQ#is asserted when the agent has won the bus. An example of arbitration flow is shown below inTable 7-4.Table 7-4.Arbitration FlowCycle0EventThe arbiter is currently driving Master_A’s GNT#. The arbitration flow is independent ofwhether or not Master_A is involved with a transaction. For example, the PCI bus could beparked with Master_A.Master_B asserts its REQ# for PCI bus ownership. The arbitration logic calculates that1Master_B has a higher priority than Master_A.2 The arbiter deasserts GNT# for Master_A since Master_B is higher priority.3 The arbiter asserts GNT# for Master_B.4When Master_B drives FRAME#, any of the priority winners that were not granted the busare promoted to a higher priority level when the reserved promotion slot is unoccupied(Section 7.2.1.1, “Priority Mechanism” on page 7-3).1. Rule 2 above, indicates that the idle state must be monitored on the PCI bus. The arbiter always asserts a master’s GNT# one cycle afterdeasserting another master’s GNT# so the idle state is unimportant.Developer’s Manual 7-7