Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.19 ATU Maximum Latency Register - ATUMLATATU Maximum Latency Register bit definitions adhere to PCI Local Bus Specification,Revision 2.2. This register specifies how often the device needs to access the PCI bus in incrementsof 8 PCI clocks.This register and the Minimum Grant Register are information-only registers which theconfiguration uses to determine how often a bus master typically requires access to the PCI bus andthe duration of a typical transfer when it does acquire the bus. This information is useful indetermining the values to be programmed into the bus master latency timers and in programmingthe algorithm to be used by the PCI bus arbiter.Table 5-47.ATU Maximum Latency Register - ATUMLATIOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesrorororororororoIntel ® 80200 Processor Local Bus Address123FHPCI Configuration Address Offset3FHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07:00 00HSpecifies frequency (how often) the device needs to access the PCI bus in increments of 8 PCI clocks. Azero value indicates the device has no stringent requirement.5-80 Developer’s Manual