Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipMemory ControllerFigure 3-2 illustrates how two Flash devices would interface with the Intel ® 80312 I/O companionchip through the MCU.Figure 3-2.Four Mbyte Flash Memory SystemRAD(2:0)A(2:0)RAD(8:3)A(8:3)LatchA(22:17)Intel ® 28F016-7016-Mbit FlashIntel ® 80312I/O CompanionChipRAD(16:9)LatchA(16:9)A(20:0)OE#RALERAD(16:0)ROE#WE#DQ(7:0)CE#REW#RCE0#RCE1#Intel 28F016-7016-Mbit FlashA(20:0)OE#WE#DQ(7:0)CE#A8265-013-6 Developer’s Manual
Intel ® 80312 I/O Companion ChipMemory Controller3.2.2.1 Flash Memory AddressingSince the internal bus comprises a 64-bit data bus, it is possible that an internal bus master requestsup to 8 bytes for a read transaction.The Flash interface utilizes an externally multiplexed address/data bus. The address bus iseffectively 23 bits. The memory controller pipelines the address in two cycles. During the firstaddress phase, address bits [22:9] are presented on RAD[16:3]. An external 14-bit latch mustpreserve RAD[16:3] using RALE. During the second address phase, address bits [8:0] arepresented on RAD[8:0]. The data bus is multiplexed on RAD[16:9]. The MCU increments thelower 3 address bits (RAD[2:0]) throughout the subsequent data phases.The two Flash chip enables (RCE[1:0]#) support a Flash memory subsystem consisting of twodevices. The base addresses for the two Flash devices are programmed in FEBR0 and FEBR1. Thesize of each Flash memory region is programmed in FBSR0 and FBSR1.To determine when the internal bus address is within Flash memory space, Table 3-3 indicateswhich bits of the FEBRx are compared with the corresponding bits of I_AD[31:0].Table 3-3.Address Decoding for Flash Memory SpaceFlash Bank SizeBits Compared for Decoding the Flash Address Range64 Kbytes FEBRx[31:16]128 Kbytes FEBRx[31:17]256 Kbytes FEBRx[31:18]512 Kbytes FEBRx[31:19]1 Mbyte FEBRx[31:20]2 Mbytes FEBRx[31:21]4 Mbytes FEBRx[31:22]8 Mbytes FEBRx[31:23]A valid address range for RCE[0]# is defined by the start address programmed in the base addressregister (FEBR0) with the ending address determined by the size programmed into the bank sizeregister (FBSR0). The programmed value in the base address register requires alignment based onthe size programmed into the FBSR0 register. The base address logic ignores the lower address bitsbased on the programmed block size. For example, when the memory size is 2 Mbytes, thesoftware programs the base address value aligned with a 2 Mbyte boundary.RCE[1]# follows the same logic but uses FEBR1 and FBSR1.Refer to Section 3.2.5, “Overlapping Memory Regions” on page 3-33 for prioritization detailswhen the two Flash memory regions overlap.Developer’s Manual 3-7
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