Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.49 Secondary ATU Queue Control Register - SAQCRThe Secondary ATU Queue Control Register contains programmable parameters affectingoperation of the secondary ATU queues.Table 5-77.Secondary ATU Queue Control Register - SAQCRIOPAttributesrv31rvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rv rv rv rvPCIAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrw rwrvrvrvrvIntel ® 80200 Processor Local Bus Address12B8HPCI Configuration Address OffsetB8H - BBHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:06 00H Reserved05:04 00 2Memory Write Non-Full State - these bits define the definition of what a non-full state is for the secondaryATU inbound posted memory write queue (S_IWQ).00 - A non-full queue has 8 bytes or more free10 - A non-full queue has 32 bytes or more free11 - Reserved (treated like 00)These bits define when the PCI interface of the secondary ATU accepts a posted memory write operationbased on the number of bytes in a queue.03:00 0H ReservedDeveloper’s Manual 5-113