Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.2 Theory of OperationThe DMA Controller provides three channels of high throughput PCI-to-Memory transfers.Channels 0 and 1 transfer blocks of data between the primary PCI bus and the Intel ® 80200processor local memory.Channel 2 transfers blocks of data between the secondary PCI bus and the Intel ® 80200 processorlocal memory. All channels operate identically. Each channel has a PCI bus interface and aninternal bus interface. Figure 9-2 shows the block diagram for one channel of the DMA Controller.Figure 9-2.DMA Channel Block DiagramDMA ChannelData QueueDataAlignmentUnit64-bitPCI BusMaster PCIBus InterfaceControl RegistersInternalBus Interface64-bitInternal BusChannel Control RegisterChannel Status RegisterDescriptor Address RegisterNext Descriptor Address RegisterPCI Address RegisterPCI Upper Address RegisterIntel ® 80200 Processor Local AddressByte Count RegisterDescriptor Control RegisterEach DMA channel uses direct addressing for both the PCI bus and the internal bus. It supportsdata transfers to and from the full 64-bit address range of the PCI bus. This includes 64-bitaddressing using PCI DAC command. The channel provides a special register which contains theupper 32 address bits for the 64-bit address. The DMA channels do not support data transfers thatcross a 32-bit address boundary.Both the PCI interface and the internal bus interface support large burst lengths up to 4 KBytes.The channel programming interface is accessible from the internal bus through a memory-mappedregister interface. Each channel is programmed independently and has its own set of registers. ADMA transfer is configured by writing the source address, destination address, number of bytes totransfer, and various control information into a chain descriptor in the Intel ® 80200 processor localmemory. Chain descriptors are described in detail in Section 9.3.Each channel supports chaining. Chain descriptors that describe one DMA transfer each can belinked together in the Intel ® 80200 processor local memory to form a linked list. Each chaindescriptor contains all the necessary information for transferring a block of data in addition to apointer to the next chain descriptor. The end of the chain is indicated when the pointer is zero.Each channel contains a hardware data alignment unit. This unit enables data transfers from or tounaligned addresses in either the PCI address space or the Intel ® 80200 processor local addressspace. All combinations of unaligned data are supported with the data alignment unit.The DMA Controller supports 64-bit and 32-bit wide PCI bus widths. Refer to Section 9.4 foradditional information on various PCI bus width transfer mechanisms.Developer’s Manual 9-3