Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.3.2 64-Bit Operation with 32-Bit TargetsWhen a 64-bit transfer is requested by the PCI master interfaces by the assertion of REQ64#, itisnot guaranteed that the target of the transaction is capable of performing the 64-bit request. Whenthe target is not 64-bit capable, ACK64# will remain deasserted when the target asserts DEVSEL#to claim the transaction. When a target signals that it cannot complete the transaction using 64-bittransfers, the bridge master interfaces are responsible for completing the transactions as a 32-bitmaster. Two possible conditions arise from a 32-bit target which does not respond with ACK64#:1. ACK64# deasserted but a burst can be sustained2. ACK64# deasserted but a burst can not be sustainedWhen a 32-bit target does not respond with ACK64# and STOP#, it is capable of continuing a burst asa 32-bit target. For memory read requests, the bridge master interfaces changes to 32-bit operationby only expecting read data on the lower byte lanes, AD[31:0]. The master interfaces continuerequesting read data (by the continued asserting of IRDY#) as 32-bit masters. No mastercompletions are prematurely signaled due to 32-bit target response. For memory write operations,the master interface may already have the first data phase on the bus by the time it is detected thatACK64# has not been asserted. The bridge Primary/Secondary master interface discontinuesdriving data on the upper 4 bytes during the second data phase. The second data phase of the burstnow contains the data from the high 4 bytes of the first data phase. The master interface stopsdriving the AD[63:32] and C/BE[7:4]# during data phase 2 and all subsequent data phases of theburst write transfer. See Figure 4-10 for a diagram of this transaction. As a note, a disconnect afterthe first data phase of the burst transfer write will result in the continuation of the write transactionas a 32-bit master only (no REQ64#). This works similar to the write transfer disconnected in thefirst data phase described in the next paragraph.When a 32-bit target does not respond with ACK64# but asserts STOP#, the target will not continuethe burst. When a read or write request is made and STOP# without TRDY# is signaled (Retry),the master interface must repeat the original read or write request as a 64-bit transaction. When thetarget signals a Disconnect with data (STOP# and TRDY#) on a write transaction, then only thelower four bytes of the 8-byte transfer have been delivered. The master state machines of the bridgeunit repeat the request as a 32-bit master (no REQ64# assertion) using the upper four bytes of datafrom the disconnected transaction on AD[31:00] and the next address (i.e., when address 00H wasused in the first 64-bit request, address 04H is used in the next 32-bit request). The bridge unitcompletes the memory write transaction as a 32-bit master until the data transferred from theinitiating interface is exhausted (data from the posted memory write being completed on the targetbus) regardless of the number of times the target disconnects the master or the address boundary onwhich it occurs. This occurs for 64-bit requests which are disconnected with no ACK64#. 64-bitrequests disconnected with an ACK64# are continued as 64-bit requests. When the target signals aDisconnect with data on a read transaction (during the first data phase), then data has only beenreturned on AD[31:00]. No additional read requests are initiated due to delayed read transactionusage (See Section 4.6.5 for details).Note that 32-bit targets create special circumstances for FRAME# signaling. For 32-bit, singleDword transfers, FRAME# is driven low and then high immediately in the next clock signalinglast data phase. Due to the potential of requiring two 32-bit data phases to complete what wasoriginally intended as one 64-bit data phase, this is not possible. FRAME# must not be deasserteduntil after ACK64# is returned.4-34 Developer’s Manual