Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.10 PCI Transaction TerminationPCI creates a mechanism for both PCI initiators and PCI targets to prematurely terminate atransaction. As a PCI master (initiator), a device can terminate a transaction when it is complete orwhen an error condition occurs. As a slave (target), a PCI device can only terminate when an errorcondition occurs. While transaction termination can be initiated by either a master or a target,ultimately it is up to the master to bring a PCI transaction to an orderly conclusion. As a bridgedevice, the target interface is responsible for this on the target bus. A PCI transaction is consideredconcluded when both FRAME# and IRDY# are both deasserted indicating a PCI IDLE cycle.4.10.1 Termination as a Master (Initiator)The target interface of the bridge unit, acting as a PCI master, will terminate a PCI transactionunder the different situations described in the following sections.4.10.1.1 Completion4.10.1.2 Time-outThe target interface will complete the transaction in response to a completion on the initiatinginterface. Completion termination occurs when the initiator bus has FRAME# and IRDY#deasserted. FRAME# will always be deasserted during the second to last data transfer of atransaction. Refer to the PCI Local Bus Specification,Revision2.2.A time-out occurs when the GNT# signal is deasserted on the target bus and the associated masterlatency timer has expired (see Section 4.6.2.1). A normal termination will occur on the targetinterface (except when Memory Write and Invalidate is in progress). See the next section for theMemory Write and Invalidate case.4.10.1.3 Time-out During Memory Write and InvalidateWhen target interface time-out occurs during a Memory Write and Invalidate transaction, thebridge will retain ownership until an entire cacheline has been transferred from the PMW Queues.Refer to the PCI Local Bus Specification, Revision2.2.Developer’s Manual 4-63