Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.4.13 M3_D1_gntThis occurrence event monitors the number of times PCI Master 1 is granted the PCI bus. Itincrements the counter when the device is the PCI bus master. The counter is incremented once forevery new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.4.14 M3_D2_gntThis occurrence event monitors the number of times PCI Master 2 is granted the PCI bus. Itincrements the counter when the device is the PCI bus master. The counter is incremented once forevery new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11.3.5 Mode 4: Secondary PCI Bus and External AgentsProgramming Mode4 (M4) in the ESR enables performance monitoring on the secondary PCI bus.In addition, performance monitoring is done for external agents (Intel ® 80312 I/O companion chip,Master3, Master4 and Master5) on the PCI bus. Master3 indicates the external PCI device that isconnected to the REQ3 and GNT3 signals of the internal arbiter in the Intel ® 80312 I/O companionchip. The nomenclature is similar for all other external PCI masters; Master 1 through Master 5.All counters are clocked at the secondary PCI bus frequency. The following sections describe themonitored events in Mode 4.11.3.5.1 M4_SPCIbus_idleThis duration event increments the counter every PCI idle cycle. An idle cycle occurs when there isno activity on the bus due to data being transferred and/or the bus is not in an overhead cycle. Anoverhead cycle is a cycle when a master owns the bus, however the master is unable to send data orthe target is unable to receive data - hence no data is transferred.11.3.5.2 M4_SPCIbus_busyThis duration event increments the counter every PCI data cycle. Data cycles comprise of twoinstances:11.3.5.3 M4_D3_acq• The Intel ® 80312 I/O companion chip as a master on the bus is involved in data transfers toother masters.• External masters initiate data transfers to either the Intel ® 80312 I/O companion chip or toother masters on the bus.This duration event counts the number of clocks spent by PCI Master 3 acquiring the PCI interface.The counter increments on every clock cycle after the device has requested use of the PCI bus buthas not actively driven the PCI bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to PCI Master 3) to calculate the average acquisition latency for the device.Developer’s Manual 11-13