Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80312 I/O Companion Chip Arbitration7.2.1.5 Secondary PCI Bus Arbitration ParkingArbitration parking occurs when the arbiter asserts GNT# to a selected PCI bus agent and no agentis currently using or requesting the bus.Upon reset, the internal arbiter parks the internal bus with the CIU and the SARB parks thesecondary PCI bus with the bridge. After a master requests, and is granted the bus, the arbiter parksthe bus with that master. In other words, the last master that was granted the bus is responsible forparking.When the secondary PCI bus is parked, the last master continues to assert S_AD[31:0],S_C/BE[3:0]#, andS_PAR. This prevents the PCI bus from floating.Note:The 64-bit extension signals (S_AD[63:32], S_C/BE[7:4]#,andS_PAR64) are not actively drivenwhen the secondary PCI bus is parked on the Intel ® 80312 I/O companion chip. Per the PCI LocalBus Specification, Revision 2.2, pull-ups provided on the motherboard ensure that these signals arestable.When a PCI bus is parked during an idle state, the parked agent loses the bus when the arbiterasserts another agent’s GNT#. The parked agent relinquishes the bus and stops driving the addressand command signals in one clock and parity one clock after that (for the secondary PCI bus).When the arbiter removes GNT# and simultaneously an agent drives FRAME# on the bus, theagent completes the initiated bus transaction.7.2.2 Atomic AccessesThe Intel ® 80312 I/O companion chip is capable of performing atomic operations to the memorysubsystem. Since the CIU (Chapter 8, “Intel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit”)andMCU(Chapter 3, “Memory Controller”)resideontheinternal bus, the arbiter provides a mechanism for guaranteeing that no other master may accesslocal memory while the Intel ® 80200 processor is performing an atomic operation.7.2.3 Internal and Secondary PCI Arbiter DifferencesThere is one difference between the secondary arbiter (SARB) and the internal bus arbiter (IARB):• The internal arbiter maintains a Multi-Transaction Timer (MTT) for the CIUThe Intel ® 80200 processor has an inherently small burst size. For this reason, a busy internal buscould inhibit data traffic for the Intel ® 80200 processor. To address this issue, the IARBimplements a Multi-Transaction Timer (MTT) which allocates a minimum timeslice where theIARB keeps GNT[8]# asserted. Refer to Section 7.2.3.1, “Multi-Transaction Timer” on page 7-9for details.7-8 Developer’s Manual