Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.3.2 Power Failure SequenceFigure 3-20 illustrates the sequence of events during a power failure as defined by PCI Local BusSpecification, Revision2.2.Figure 3-20.Power Failure SequenceCLKPOWERPWRGOODP_RST#approximately 1 msPULLCKESCKE outSCKEInitialPower-UpPower DetectedGood by SupplySystem Power FailureDeasserts ResetPower Restored3.3.2.1 Power Failure Impact on the SystemUpon initial power-up a power supply provides the appropriate voltage to the system. The voltagelevel increases at a rate that is dependent on the type of power supply used and the components inthe system. These variables are not certain, so the power supply often provides a signal calledPWRGOOD which indicates the time when the voltage has reached a reliable level. The powersupply deasserts PWRGOOD when the voltage level drops below a certain minimum threshold.PCI Local Bus Specification, Revision 2.2 indicates that once PWRGOOD is deasserted, the PCIreset pin (P_RST#) is asserted in order to float the output buffers. In the specification T fail isdefined as the time when P_RST# is asserted in response to the power rail going out ofspecification. T fail is the minimum of:• 500 ns from either power rail going out of specification (exceeding specified tolerances bymore than 500 mV)• 100 ns from the 5 V rail falling below the 3.3 V rail by more than 300 mV3.3.2.2 System AssumptionsThis proposal makes specific assumptions about the system behavior during a power failure. Whenthe below assumptions are not guaranteed, it is the vendor’s responsibility to ensure them.1. P_RST# is asserted to the Intel ® 80312 I/O companion chip when there is at least 1 µs ofreliable power remaining and stays asserted as long as reliable power is available. This isrequired so the memory controller can execute its power-failure state machine in response tothe assertion of P_RST#.2. The PCI clock continues to run for at least 20 clock cycles after P_RST# is asserted. TheIntel ® 80312 I/O companion chip requires a PCI clock operating in the specified range of16-66 Mhz in order to complete the power fail sequence and put SDRAM in self-refresh mode.3-36 Developer’s Manual