Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit• The channel shall cease data transfers for the current chain descriptor and clear the ChannelActive flag in the CSR.• The channel invalidates any data held in the queue and not read any new chain descriptors.• The channel sets the appropriate error flag in the Channel Status Register. For example; whena PCI Master-Abort occurred during a DMA transfer, the channel sets bit 3 in the CSR. Duringan MWI transaction, the channel completes the transfer of the cache line before stopping.• The channel also signals an interrupt to the Intel ® 80200 processor.• The channel does not restart a DMA transfer after any error condition. It is the responsibilityof the application software to configure the channel to complete any remaining transfers.Note:IB errors (Target-abort only) that occur while a DMA channel is the master on the internal bus arerecorded by the MCU and interrupt the Intel ® 80200 processor. For correct operation of the DMAchannel, user software has to disable the channel before clearing the error condition. Further, thechannel needs to be re-enabled by writing a 1 to CCR.ce before initiating a new operation.Accesses to the MCU can be 64-bits or smaller. In both cases, there are three possible scenarios formulti-bit ECC errors on reads or writes. These errors conditions are handled as detailed below:• Multi-bit ECC error on MCU Data Read: Refer to Chapter 3, “Memory Controller” forcomplete details regarding error handling.• Multi-bit ECC error on MCU Data Write: This instance covers the case where the first datawrite is less than a 64-bit value forcing the MCU to execute a read-modify-write operation.Refer to Chapter 3, “Memory Controller” for complete details regarding error handling.• Multi-bit ECC error on MCU Data Write: This instance covers the case where the last datawrite is less than a 64-bit value forcing the MCU to execute a read-modify-write operation.Refer to Chapter 3, “Memory Controller” for complete details regarding error handling.9-24 Developer’s Manual