Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.4.6 M3_D0_ownThis duration event counts the duration for which PCI Master 0 is the master on the PCI interface.The counter increments on every clock cycle during which PCI Master 0 is the bus master.11.3.4.7 M3_D1_acqThis duration event counts the number of clocks spent by PCI Master 1 acquiring the PCI interface.The counter increments on every clock cycle after the device has requested use of the PCI bus buthas not actively driven the PCI bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to PCI Master 1) to calculate the average acquisition latency for the device.11.3.4.8 M3_D1_ownThis duration event counts the duration for which PCI Master 1 is the master on the PCI interface.The counter increments on every clock cycle during which PCI Master 1 is the bus master.11.3.4.9 M3_D2_acqThis duration event counts the number of clocks spent by PCI Master 2 acquiring the PCI interface.The counter increments on every clock cycle after the device has requested use of the PCI bus buthas not actively driven the PCI bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to PCI Master 2) to calculate the average acquisition latency for the device.11.3.4.10 M3_D2_ownThis duration event counts the duration for which PCI Master 2 is the master on the PCI interface.The counter increments on every clock cycle during which PCI Master 2 is the bus master.11.3.4.11 M3_SPCI_IOP_gntThis occurrence event monitors the number of times the Intel ® 80312 I/O companion chip isgranted the secondary PCI bus. It increments the counter when the Intel ® 80312 I/O companionchip is the secondary PCI bus master. The counter is incremented once for every new transaction.For multi-cycle transactions, the counter increments once on the first cycle. The count value is asummation of the individual grants received by the bridge, satu and dma Ch-2.11.3.4.12 M3_D0_gntThis occurrence event monitors the number of times PCI Master 0 is granted the PCI bus. Itincrements the counter when the device is the PCI bus master. The counter is incremented once forevery new transaction. For multi-cycle transactions, the counter increments once on the first cycle.11-12 Developer’s Manual