Intel 80312 I/O Companion Chip - ECEE

Peripheral Memory-Mapped Registers AThis chapter describes the memory-mapped registers for the integrated peripherals.A.1 OverviewThe Peripheral Memory-Mapped Register (PMMR) interface gives software the ability to read andmodify internal control registers. Each of these registers is accessed as a memory-mapped 32-bitregister with a unique memory address. Access is accomplished through regular memory-formatinstructions from the Intel ® 80200 processor based on Intel ® XScale microarchitecture (ARM*architecture compliant).These memory-mapped registers are specific to the Intel ® 80312 I/O companion chip only. Theysupport the:• DMA Controller Unit• Memory Controller• I 2 C Bus Interface Unit• PCI and Peripheral Interrupt Controller Unit• Messaging Unit• Intel ® 80312 I/O Companion Chip Arbitration• PCI-to-PCI Bridge Unit• PCI Address Translation Unit• Performance Monitoring Unit• Application Accelerator Unit• General Purpose Input Output (GPIO)Each of these peripherals fully describe the independent functionality of the registers, control andusage.The PMMR interface provides full accessibility from the Primary ATU, Secondary ATU, and theIntel ® 80200 processor. Addresses 0000 1000H through 0000 17FFH are allocated to the PMMRinterface.Developer’s Manual A-1