Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller Unit2.7.1 PCI Interrupt Routing Select Register - PIRSRThe PCI Interrupt Routing Select Register (PIRSR) determines the routing of the external inputpins. The input pins consist of four secondary PCI interrupt inputs which are routed to either theprimary PCI interrupts or to the Intel ® 80200 processor FIQ# interrupt. The PCI interrupt pins aredefined as “level sensitive,” asserted low. The assertion and deassertion of the interrupt pins aresynchronous to the PCI or internal bus clock.Table 2-8 shows the bit definitions for programming the PCI Interrupt Routing Select Register.Table 2-8.PCI Interrupt Routing Select Register (PIRSR)IOPAttributesPCIAttributes31 28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rwseseseseldlclblana na na na na na na na na na na na na na na na na na na na na na na na na na na na rw rw rw rwIntel ® 80200 Processor Local BusAddress0000 1050HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA= Not AccessibleBit Default Description31:4 0 Reserved (initialize to 0)3 02 01 00 0S_INTD#/IRQ3 Select Bit - PIRSR, xsel0 = Interrupt routed to P_INTD# pin1 = Interrupt routed to FIQ# outputS_INTC#/IRQ2 Select Bit - PIRSR, xsel0 = Interrupt routed to P_INTC# pin1 = Interrupt routed to FIQ# outputS_INTB#/IRQ1 Select Bit - PIRSR, xsel0 = Interrupt routed to P_INTB# pin1 = Interrupt routed to FIQ# outputS_INTA#/IRQ0 Select Bit - PIRSR, xsel0 = Interrupt routed to P_INTA# pin1 = Interrupt routed to FIQ# outputDeveloper’s Manual 2-11