Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller Unit2.4.3 Intel ® 80312 I/O Companion Chip: Internal PeripheralInterrupt RoutingThe IRQ# and FIQ# interrupt inputs of the Intel ® 80200 processor receive inputs from multipleIntel ® 80312 I/O companion chip internal interrupt sources. There is one internal latch before eachof these three inputs that provides the necessary muxing of the different interrupt sources. Moredetail about the exact cause of the interrupt can be determined by reading the status register of therespective peripheral unit.2.4.3.1 FIQ1 Interrupt SourcesThe FIQ1 interrupt latch of the Intel ® 80312 I/O companion chip PCI and Peripheral InterruptController Unit receives interrupts from the three DMA channels, Performance Monitoring Unitand the Application Accelerator (AA) Unit. Each DMA channel interrupt is either for DMA End ofTransfer interrupt or DMA End of Chain interrupt. A Performance Monitoring Unit interruptimplies that at least one of the fourteen programmable event counters and/or the Global TimeStamp Counter has a pending interrupt condition. An AA interrupt implies an End of Chaininterrupt or an End of Transfer interrupt.A valid interrupt from any of these sources sets the bit in the latch and outputs a level-sensitiveinterrupt to the Intel ® 80312 I/O companion chip FIQ# output pin. The interrupt latch shouldcontinue driving an active low input to the processor interrupt input as long as a one is present inthe latch. The FIQ1 Interrupt Latch is read through the FIQ1 Interrupt Status Register. The FIQ1Interrupt Latch is cleared by clearing the source of the interrupt at the internal peripheral.The interrupt sources which drive the inputs to the FIQ1 Interrupt Latch are detailed in Table 2-3.Table 2-3.FIQ1# Interrupt SourcesUnit Interrupt Condition RegisterDMA Channel 0DMA Channel 1DMA Channel 2Application AcceleratorPerformance MonitorEnd of Chain 9.14.2 Channel Status Register - CSR (pg. 9-27)End of Transfer 9.14.2 Channel Status Register - CSR (pg. 9-27)End of Chain 9.14.2 Channel Status Register - CSR (pg. 9-27)End of Transfer 9.14.2 Channel Status Register - CSR (pg. 9-27)End of Chain 9.14.2 Channel Status Register - CSR (pg. 9-27)End of Transfer 9.14.2 Channel Status Register - CSR (pg. 9-27)End of Chain 10.11.2 Accelerator Status Register - ASR (pg. 10-25)End of Transfer 10.11.2 Accelerator Status Register - ASR (pg. 10-25)Counter Overflow11.6.3 Event Monitoring Interrupt Status Register(EMISR) (pg. 11-25)Developer’s Manual 2-5