Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.6 ATU Error ConditionsPCI and internal bus error conditions cause the ATU state machines to exit normal operation andreturn to idle states. In addition, status bits are set to inform error handling code of the exact causeof the error condition. The Intel ® 80312 I/O companion chip ATUs use a similar error handlingscheme for PCI interrupts as the PCI to PCI Bridge Unit. All of the Messaging Unit errors arereported in the same manner as PATU errors. Error conditions and status can be found in thePATUSR and the PATUISR. The basic flow for a PCI error is as follows:• Set the bit in the ATU Status Register which corresponds to the error condition (master abort,target abort, etc.)• Set the bit in the ATU Interrupt Status Register which corresponds to the error condition(master abort, target abort, etc.). This function is maskable for all PCI error conditions.• The setting of the bit in the ATU Interrupt Status Register results in a IRQ# interrupt beingdriven to the Intel ® 80200 processorError conditions on one side of the ATU are generally propagated to the other side of the ATU andhave different effects depending on the error. Error conditions and their effects are described in thefollowing sections.PCI bus error conditions and the action taken on the bus are defined within the PCI Local BusSpecification, Revision 2.2. The ATU adheres to the error conditions defined within the PCIspecification for both master and slave operation. Error conditions on the internal bus are caused byan ECC error from the Memory Controller (see Section 3.4, “Interrupts/Error Conditions” onpage 3-41 for details on memory controller error conditions) or by incorrect addressing resulting inan internal master abort. All actions on the PCI Bus for error situations are dependent on the errorcontrol bits found in the Primary ATU and Secondary ATU Control Registers. See Section 5.7,“Register Definitions” on page 5-55.The following sections detail all ATU error conditions on the PCI bus and the Intel ® 80312 I/Ocompanion chip internal bus, action taken on these conditions, and the status and control bitsassociated with error handling.Developer’s Manual 5-39