Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.3.1 Chain DescriptorsAll DMA transfers are controlled by chain descriptors located in local memory. A chain descriptorcontains the necessary information to complete one data transfer. A single DMA transfer has onlyone chain descriptor in memory. Chain descriptors can be linked together to form more complexDMA operations.To perform a DMA transfer, one or more chain descriptors must first be written to Intel ® 80200processor local memory. Figure 9-3 shows the format of an individual chain descriptor. Everydescriptor requires six contiguous words in Intel ® 80200 processor memory and is required to bealigned on an 8-word boundary. All six words are required.Each word in the chain descriptor is analogous to control register values. Bit definitions for thewords in the chain descriptor are the same as for the DMA control registers.• The first word is the Intel ® 80200 processor memory address of the next chain descriptor. Avalue of zero specifies the end of chain. This value is loaded into the Next Descriptor AddressRegister. Because chain descriptors must be aligned on an 8-word boundary, the channel mayignore bits 04:00 of this address.• The second word is the lower 32-bit PCI source/destination address. This address is generatedon the PCI bus. This value is loaded into the PCI Address Register.• The third word is the upper 32-bit PCI source/destination address, when needed. This addressis used during Dual Address Cycles for driving 64-bit PCI addresses. The address is ignoredwhen DAC is disabled. This value is loaded into the PCI Upper Address Register.• The fourth word is the Intel ® 80200 processor source/destination address. This address isdriven on the internal bus. This value is loaded into the Intel ® 80200 processor Local AddressRegister.• The fifth word is the Byte Count value. This value determines the number of bytes to transfer.This value is loaded into the Byte Count Register.• The sixth word is the Descriptor Control word. This word configures the DMA channel forone DMA transfer. It contains the PCI command type, which determines the direction of thedata transfer. This value is loaded into the Descriptor Control Register.There are no data alignment requirements for either the PCI address or the Intel ® 80200 processoraddress.Refer to Section 9.14 for additional descriptions about the DMA Controller registers.Developer’s Manual 9-5