Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.45 Secondary Outbound Configuration Cycle AddressRegister - SOCCARThe Secondary Outbound Configuration Cycle Address Register is used to hold the 32-bit PCIconfiguration cycle address. The Intel ® 80200 processor writes the PCI configuration cyclesaddress which then enables the secondary outbound configuration read or write. The Intel ® 80200processor then performs a read or write to the Secondary Outbound Configuration Cycle DataRegister to initiate the configuration cycle on the secondary PCI bus.Table 5-73.Secondary Outbound Configuration Cycle Address Register - SOCCARIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rwPCIAttributesrorororororororororororororororororororororororororororororororoIntel ® 80200 Processor Local Bus Address12A8HPCI Configuration Address OffsetA8H - ABHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:00 0000 0000HSecondary Configuration Cycle Address - These bits define the 32-bit PCI address used during anoutbound configuration read or write cycle.Developer’s Manual 5-109