Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.4.4 Type 1 to Special Cycle ConversionA Type 1 configuration write command on the Primary interface will be converted to a SpecialCycle command on the Secondary interface provided all of the following conditions are met:• Device Number is all ones - P_AD[15:11] = 11111 2• Function Number is all ones - P_AD[10:8] =111 2• Register Number is all zeros - P_AD[7:2] = 00000 2• Bus Number matches the Secondary Bus Number of the bridgeAll PCI devices ignore the address during a Special Cycle and a Master-Abort occurs on the PCIbus. However, the Master Abort error status bit (bit 13 of the Secondary Status Register) is not set.The data for the Special Cycle on the Secondary interface will be the write data from the Type 1command on the Primary interface. Converted cycles are restricted to a burst length of one PCI32-bit data phase.A Type 1 configuration write command on the Secondary interface will be converted to a SpecialCycle command on the Primary interface provided all of the following conditions are met:• Device Number is all ones - S_AD[15:11] = 11111 2• Function Number is all ones - S_AD[10:8] = 111 2• Register Number is all zeros - S_AD[7:2] = 00000 2• Bus Number matches the Primary Bus Number of the bridgeThe address during a Special Cycle is ignored by all PCI devices and a Master-Abort occurs on thePCI bus. However, the Master Abort error status bit (bit 13 of the Primary Status Register) is notset. The data for the Special Cycle on the Primary interface will be the write data from the Type 1command on the Secondary interface. Converted cycles are restricted to a burst length of one 32-bitPCI data phase.4-12 Developer’s Manual