Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.4 Primary Status Register - PSRPrimary Status Register bits adhere to the definitions in the PCI Local Bus Specification,Revision 2.2 but only apply to the Primary interface of the bridge. The read/clear bits can only beset by the internal hardware and are cleared by either a reset condition of by writing a 1 2 to theregister.Table 4-27. Primary Status Register - PSR (Sheet 1 of 2)IOPAttributes15 12 8 4 0rc rc rc rc rc ro ro rc ro ro ro ro rv rv rv rvPCIAttributesrcrcrcrcrcrororcrororororvrvrvrvPCI Configuration Offset06 - 07HIntel ® 80200 Processor Local Bus Address0000 1006HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default DescriptionDetected Parity Error - This bit is set when a parity error is detected during a data transfer on the Primarybus even when parity handling is disabled. Set under the following conditions:• Write Data Parity Error when the Primary interface of the Bridge is a slave (downstream write).15 0 2• Read Data Parity Error when the Primary interface of the Bridge is a master (upstream read).• Any Address Parity Error on the Primary Bus (including one generated by the Primary interface ofthe Bridge).14 0 2 Signaled System Error - This bit is set when P_SERR# is asserted on the Primary bus.Master Abort - This bit is set whenever a transaction initiated by the bridge on the Primary bus (except13 0 2 Special Cycles) ends in a Master-Abort.Target Abort (master) - This bit is set whenever a transaction initiated by the Primary interface ends in a12 0 2 Target-Abort.Target Abort (target) - This bit is set whenever the bridge, acting as a target, terminates the transaction11 0 2 on the Primary bus with a Target-Abort.10:09 10 2DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# timing for a target device(except configuration accesses).00 2 =Fast01 2 =Medium10 2 =Slow11 2 = ReservedIn general, the Primary interface uses Medium timing.However, When the bridge Special Memory Window is enabled (see Section 4.5.4.1, “Special Externaldecode timing.Though this occurrence is not part of the normal bridge operation, the PCI Local Bus Specification,Revision 2.2 requires that this field of the status register indicate the slowest DEVSEL# possible by atarget device.In the event that a subtractive decode agent is present on the bridge primary bus interface, the indicationthat the bridge could claim positively with Slow decode will prevent the users of this bus fromprogramming the subtractive decode agent to claim with Slow decode timing.With the exception of Primary Interface Slow Decode under certain, special conditions, the performanceofthebridgewillnot be affected.4-88 Developer’s Manual