Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.7 ATU Cacheline Size Register - ATUCLSRCacheline Size Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2. Thisregister is programmed with the system cacheline size in DWORDs (32-bit words). Cacheline Sizeis restricted to either 0, 8 or 16 DWORDs; the ATU interprets any other value as “0”.Table 5-34.ATU Cacheline Size Register - ATUCLSRIOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesrw rw rw rw rw rw rw rwIntel ® 80200 Processor Local Bus Address120CHPCI Configuration Address Offset0CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearBit Default Description07:00 00HATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted toeither 0, 8 or 16 DWORDs.5-68 Developer’s Manual