Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation UnitThe following action with the given constraints are performed by the primary and secondary ATUswhen a master abort is detected by the internal master interface during an inbound read transaction:Table 5-19.Master Abort During an Inbound Read TransactionPrimary ATUSet the Internal Bus Master Abort bit (bit 7) in thePATUISRReturn a master abort condition to the initiatingmaster during the delayed completion cycle on theprimary PCI bus. No data is ever read from theinternal bus and returned to the primary PCI bus.Flush the transaction that was master aborted fromthe P_ITQ after the master abort is delivered on thePCI interface.Secondary ATUSet the Internal Bus Master Abort bit (bit 7) in theSATUISRReturn a master abort condition to the initiatingmaster during the delayed completion cycle on thesecondary PCI bus. No data is ever read from theinternal bus and returned to the secondary PCI bus.Flush the transaction that was master aborted fromthe S_ITQ after the master abort is delivered on thePCI interface.The Internal Bus Master Abort bit is non-maskable and always results in an IRQ# interrupt beingdriven to the Intel ® 80200 processor.As a slave device on the internal bus, the ATUs can return a master abort to the CIU in response toa master abort seen on the PCI interface during a delayed read cycle. In this scenario, the masterabort is detected on the PCI interface during the read. Once this occurs, the ATU notifies theinternal bus arbiter to allow the CIU to acquire the bus, the ATU fails to claim the transaction,signalling a master abort to the internal bus master (the CIU). No error conditions are recorded bythe slave interface of the ATUs during master abort operations, since they are already recorded bythe PCI interface.Developer’s Manual 5-49