Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2 Theory of OperationThe Intel ® 80312 I/O companion chip memory controller translates the internal bus transactionsinto the protocol supported by the connected memory subsystem. The supported memorycomponents consist of SDRAM and/or Flash memory devices.3.2.1 Functional BlocksThe memory controller logically comprises the blocks illustrated in Figure 3-1:Figure 3-1.Memory Controller Block DiagramFlash Address& ControlFlashStateMachineExternal Memory Data Bus / ECCSDRAM Address& ControlSDRAMStateMachineRefreshCounterPipelining Queues andError Correction LogicConfigurationRegistersAddress &DataInternal Bus InterfaceAddressDecodeInternal BusInternal Bus Address & Control SignalsInternal BusA8067-01Developer’s Manual 3-3