Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7 Register DefinitionsEvery PCI device implements its own separate configuration address space and configurationregisters. The PCI Local Bus Specification, Revision 2.2 requires that configuration space be256 bytes, and the first 64 bytes must adhere to a predefined header format.Figure 5-10 defines the header format. Table 5-13 shows the PCI configuration registers, listed byinternal bus address offset. Table 5-14 shows the entire ATU configuration space (including headerand extended registers) and the corresponding section that describes each register. Note that allconfiguration read and write transactions are accepted on the internal bus as 32-bit transactions.Refer to Appendix A, “Peripheral Memory-Mapped Registers”.Figure 5-10.ATU Interface Configuration Header FormatATU Device ID Vendor ID 00HPrimary Status Primary Command 04HATU Class Code Revision ID 08HReserved Header Type Latency Timer Cacheline Size 0CHPrimary Inbound ATU Base Address10H14H18H1CHReserved20H24H28HATU Subsystem ID ATU Subsystem Vendor ID 2CHExpansion ROM Base Address30HCapabilities Pointer38HMaximum Latency Minimum Grant Interrupt Pin Interrupt Line 3CHPrimary and secondary ATUs are programmed via a Type 0 configuration command on the primaryinterface. See Section 5.2.1.4, “Inbound Configuration Cycle Translation” on page 5-13). ATUconfiguration space is function number one of the Intel ® 80312 I/O companion chip multi-functionPCI device. (Refer to Section 5.2.4, “PCI Multi-Function Device Swapping/Disabling” onpage 5-24 for exceptions to this statement.)Beyond the required 64 byte header format, ATU configuration space implements extended registerspace in support of the units functionality. Refer to the PCI Local Bus Specification, Revision 2.2for details on accessing and programming configuration register space.The ATU unit includes an 8 byte extended capability configuration space beginning atconfiguration offset 80H. The extended configuration space can be accessed by a device on theprimary interface through a mechanism defined in the PCI Local Bus Specification, Revision 2.2.34HDeveloper’s Manual 5-55