Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.2 Theory of OperationThe I 2 C bus defines a serial protocol for passing information between agents on the I 2 C bus usingonly a two pin interface. The interface consists of a Serial Data/Address (SDA) lineandaSerialClock Line (SCL). Each device on the I 2 C bus is recognized by a unique 7-bit address and canoperate as a transmitter or as a receiver. In addition to transmitter and receiver, the I 2 C bus uses theconcept of master and slave. Table 12-1 lists the I 2 C device types.Table 12-1.I 2 C Bus DefinitionsI 2 C DeviceTransmitterReceiverMasterSlaveMulti-masterArbitrationDefinitionSends data to the I 2 Cbus.Receives data from the I 2 Cbus.Initiates a transfer, generates the clock signal, and terminates the transactions.The device addressed by a master.More than one master can attempt to control the bus at the same time without corruptingthe message.Procedure to ensure that, when more than one master simultaneously tries to control thebus, only one is allowed. This procedure ensures that messages are not corrupted.As an example of I 2 C bus operation, consider the case of the Intel ® 80312 I/O companion chipacting as a master on the bus (see Figure 12-1). The Intel ® 80312 I/O companion chip, as a master,addresses an EEPROM as a slave to receive data. The Intel ® 80312 I/O companion chip is amaster-transmitter and the EEPROM is a slave-receiver. When the Intel ® 80200 processor basedon Intel ® XScale microarchitecture (ARM* architecture compliant) reads data, the Intel ® 80312I/O companion chip is a master-receiver and the EEPROM is a slave-transmitter. In both cases, themaster generates the clock, initiates the transaction and terminates it.Figure 12-1.I 2 C Bus Configuration ExampleIntel ® 80312I/O CompanionChipEEPROMSCLSDAGateArrayMicrocontrollerThe I 2 C bus allows for a multi-master system, which means more than one device can initiate datatransfers at the same time. To support this feature, the I 2 C bus arbitration relies on the wired-ANDconnection of all I 2 C interfaces to the I 2 C bus. Two masters can drive the bus simultaneouslyprovided they are driving identical data. The first master to drive SDA high while another masterdrives SDA loses the arbitration. The SCL line consists of a synchronized combination of clocksgenerated by the masters using the wired-AND connection to the SCL line.12-2 Developer’s Manual