Intel 80312 I/O Companion Chip - ECEE

.Intel ® 80312 I/O Companion ChipPCI Address Translation UnitFigure 5-11.In the Primary ATU Status Register (Section 5.7.4) the appropriate bit is set indicating that theExtended Capability Configuration space is supported. When this bit is read, the device can thenread the Capabilities Pointer register (Section 5.7.14) to determine the configuration offset of theExtended Capabilities Configuration Header. The format of this header is depicted in Figure 5-11.ATU Interface Extended Configuration Header FormatPower Management CapabilitiesReservedNext Item PointerCapability IdentifierPower Management Control/Status80H84HThe first byte at the Extended Configuration Offset is the ATU Capability Identifier Register(Section 5.7.33). This identifies this Extended Configuration Header space as the type defined bythe PCI Bus Power Management Interface Specification, Revision 1.1.Following the Capability Identifier Register is the single byte Next Item Pointer Register(Section 5.7.34) which indicates the configuration offset of an additional Extended CapabilitiesHeader, when supported. In the ATU, the Next Item Pointer Register is set to 00H indicating thatthere are no additional Extended Capabilities Headers supported in the ATUs configuration space.To enable the PCI Bus Power Management Interface Specification, Revision 1.1 compliancesupport, the Power State Transition interrupt mask in bit 8 of the PATUIMR needs to be cleared andthe PCI extended Capabilities enable in bit 4 of the PATUSR needs to be set. It is the configurationsoftware responsibility to properly enable and initialize the ATUs Power Management Interfacebefore the Configuration Cycle Retry Bit in the Section 4.15.23, Extended Bridge Control Register- EBCR is cleared in order for the ATU to be Advanced Configuration and Power InterfaceSpecification, Revision 1.0 compliant.The following sections describe the ATU and Expansion ROM configuration registers.Configuration space consists of 8, 16, 24, and 32-bit registers arranged in a predefined format.Each register is described in functionality, access type (read/write, read/clear, read only) and resetdefault condition.See Section 1.4, “Terminology and Conventions” on page 1-7 for a description of reserved, readonly,andread/clear. All registers adhere to the definitions found in the PCI Local BusSpecification, Revision 2.2 unless otherwise noted.The PCI register number for each register is given in Table 5-13. As stated, a Type 0 configurationcommand on the primary bus with an active P_IDSEL or a memory-mapped internal bus access isrequired to read or write these registers.Note:Each configuration register’s access type is individually defined for PCI configuration accesses.Some PCI read-only configuration registers have read/write capability from the Intel ® 80200processor. See also Appendix A, “Peripheral Memory-Mapped Registers”.5-56 Developer’s Manual