Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.11.4 Accelerator Next Descriptor Address Register - ANDARThe Accelerator Next Descriptor Address Register (ANDAR) contains the address of the nextchain descriptor in Intel ® 80200 processor local memory for an XOR-transfer. Whenstartingatransfer, this register contains the address of the first chain descriptor. Table 10-7 depicts theAccelerator Next Descriptor Address Register.All chain descriptors are aligned on an eight 32-bit word boundary. The AAU may set bits 04:00 tozero when loading this register.Note:Table 10-7.The Accelerator Enable bit in the ACR and the Accelerator Active bit in the ASR must both beclear prior to writing the ANDAR. Writing a value to this register while the AAU is active mayresult in undefined behavior.Accelerator Next Descriptor Address Register - ANDARIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rvPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 processor local bus address180CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description00000000000Next Descriptor Address - local memory address of the next chain descriptor to be read by the31:05 00000000000Application Accelerator.00000 204:00 00000 2 ReservedDeveloper’s Manual 10-27