Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitAny PCI memory transaction present on the Secondary bus that falls outside the address rangedefined by the two register pairs (MBR-MLR and PMBR-PMLR) is forwarded upstream across thebridge from the Secondary to Primary interface. These transactions default to prefetchable unlessprogrammed to non-prefetchable in the EBCR. The Secondary interface will forward all DualAddress Cycles from the Secondary bus to the Primary bus. Dual address cycles are constrained tothe upper 4 Gbytes of the 64-bit address space (see Section 4.5.5). Under certain conditionsMemory Write and Invalidate commands can be converted to Memory Write commands (seeSection 4.6.6.4) and within the non-prefetchable address space, Memory Read Multiple andMemory Read Line commands can be converted to Memory Read commands (see Section 4.6.5).The 64-bit PCI extensions can be used by PCI memory commands for transactions initiated fromeither bridge PCI interface. See Section 4.6.3 for details on PCI 64-bit extensions. As a side note,the addition of a 64-bit PCI datapath still requires the use of DAC mode for 64-bit addressing. SeeSection 4.5.5 for details.The bridge response to memory transactions on either interface may be modified by the followingregister bits from the bridge configuration space:• Master Enable bit in the Primary Command Register (PCR)• Memory Enable bit in the Primary Command Register (PCR)• VGA Enable bit in the Bridge Control Register (BCR)The Memory Enable bit in the PCR register must be set to allow the bridge to accept memorytransactions on the Primary bus. The Master Enable bit in the PCR must be set to allow the Primaryinterface to master PCI transactions.The VGA Enable bit in the BCR register forces the bridge to forward memory accesses in theaddress range from 0A0000H to 0BFFFFH from the Primary to Secondary and blocks addresses inthe same range from Secondary to Primary. See Section 4.5.3, “VGA Address Support” onpage 4-20 for more details on VGA Compatible addressing.4.5.2.1 Burst OrderThe bridge only supports linear incrementing addresses for burst order (AD[1:0] = 00 2 ). For anyother burst order, the Bridge will disconnect the transaction after the first 32-bit data phase. SeeSection 4.8.1, “Delayed Read Transaction” on page 4-55 for information on non-linear MRLs andMRMs.4.5.2.2 Disabling the Memory Address RangeThe Memory address range can be disabled for Primary to Secondary transactions by using eitherthe Memory Enable bit or by using the MBR-MLR and PMBR-PMLR register pairs. When theMemory Enable bit in the Primary Command Register (PCR) is cleared, the Primary interface ofthe bridge will not respond to any PCI memory transaction that falls within the MBR-MLR orPMBR-PMLR register pair address ranges. The Secondary interface is unaffected by MemoryEnable bit in the PCR. In this case, all Memory transactions from the Secondary to the Primary willbe forwarded upstream through the bridge.When the Memory Limit Register (MLR) is programmed to a value less than the Memory BaseRegister (MBR) and the Prefetchable Memory Limit Register (PMLR) is programmed to a valueless than the Prefetchable Memory Base Register (PMBR), the Intel ® 80312 I/O companion chipwill not forward any transactions from the Primary to the Secondary. In this case, all Memorytransactions from the Secondary to the Primary will be forwarded upstream through the bridge.Developer’s Manual 4-19