Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.11.6 Intel ® 80200 Processor Destination Address Register - DARThe Intel ® 80200 processor Destination Address Register (DAR) contains a 32-bit, Intel ® 80200processor local memory address. This address is the destination of the XOR-transfer -Intel ® 80200processor local memory address where XOR-ed data is stored. The Intel ® 80200 processor localmemory address space is a 32-bit, byte addressable address space.Reading the DAR once the AAU has started a chain descriptor returns the current destinationaddress. For example; when the Byte Count is initially 4096 bytes and the AAU has completed theXOR-transfer operation on the first three 1K-byte data blocks, the value in the Destination AddressRegister (DAR) is the equal to the programmed descriptor value + 3072 (DAR + 3072).Table 10-9 shows the Intel ® 80200 processor Destination Address Register. This read-only registeris loaded when a chain descriptor is read from memoryTable 10-9.Intel ® 80200 Processor Destination Address Register - DARIOPAttributes31rororo28 24 20 16 12 8 4 0ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro roPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na naIntel ® 80200 processor local bus address1820HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:00 00000000H Intel ® 80200 processor Local Address - The Intel ® 80200 processor local destination address.Developer’s Manual 10-29