Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.8.2 Outbound Message Register - OMRxThere are two Outbound Message Registers: OMR0 and OMR1. When the OMR register iswritten, a PCI interrupt may be generated. The interrupt is recorded in the Outbound InterruptStatus Register and may be masked by the Outbound Message Interrupt Mask bit in the OutboundInterrupt Mask Register.Table 6-8.Outbound Message Register - OMRxPCI IOPAttributes Attributes31rw rwrw rw28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rwrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rwOMR0OMR1Intel ® 80200 Processor Local Bus Address1318H131CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:00 00000000HOutbound Message - This is 32-bit message written by the Intel ® 80200 processor.When written, an interrupt may be generated on the PCI Interrupt pin determined bythe ATU Interrupt Pin Register.Developer’s Manual 6-19