Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.5.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master1. Write IDBR: Target slave address and R/W# bit (0 for write)2. Write ICR: Set START bit, Clear STOP bit, Set Transfer Byte bit to initiate the access3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (clear)Clear IDBR Transmit Empty bit to clear the interrupt.4. Send byte 1Write IDBR: With data byte to sendWrite ICR: Clear START bit, Clear STOP bit, Enable Arb Loss interrupt, Set Transfer Byte bitto initiate the access5. Wait for Buffer empty interrupt.Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (clear)Clear IDBR Transmit Empty bit to clear the interrupt.6. Send byte 2Write IDBR: With data byte to sendWrite ICR: Clear START bit, Clear STOP bit, Set Transfer Byte bit to initiate the access7. Wait for Buffer empty interrupt.Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (clear)Clear IDBR Transmit Empty bit to clear the interrupt.8. Send repeated start as a masterWrite IDBR: Target slave address and R/W# bit (1 for read)Write ICR: Set START bit, Clear STOP bit, Disable Arb Loss interrupt, Set Transfer Byte bitthe initiate the access9. Wait for IDBR Transmit Empty interrupt. When interrupt comes.Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (set)Clear IDBR Transmit Empty bit to clear the interrupt.10. Read byte with STOPWrite ICR: Clear START bit, Set STOP bit, Enable arb loss interrupt, Set Ack/Nack bit(Nack), Set Transfer Byte bit to initiate the access11. Wait for Buffer full interrupt. When interrupt comes (Note: Unit is sending STOP).Read status register: IDBR Receive Full (set), Unit busy (set - maybe), R/W# bit (Set),Ack/Nack bit (Set)Clear IDBR Receive Full bit to clear the interrupt.Read IDBR data.Clear ICR STOP bit (optional), Clear ICR Ack/Nack Control bit (optional)Wait until Unit busy is clear before clearing the ICR SCL Enable bit. (optional)12-24 Developer’s Manual