Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller UnitTable 2-5. IRQ Interrupt Sources (Sheet 2 of 2)Unit Register Error ConditionDMA Channel 0 Channel Status Register 0DMA Channel 1 Channel Status Register 1The PCI Interrupt Routing Select Register, FIQ1 Interrupt Status Register, FIQ2 Interrupt StatusRegister, and IRQ Interrupt Status Register are described in Section 2.7.2.4.4 PCI Outbound Doorbell InterruptsPCI Master Parity ErrorPCI Target Abort (master)PCI Master AbortIB Master AbortPCI Master Parity ErrorPCI Target Abort (master)PCI Master AbortIB Master AbortPCI Master Parity ErrorPCI Target Abort (master)DMA Channel 2 Channel Status Register 2PCI Master AbortIB Master AbortApplication Accelerator Accelerator Status Register IB Master AbortMemory ControllerMemory Controller Interrupt StatusRegisterTarget-Abort (Single or Multi-bitECC Errors)The Intel ® 80312 I/O companion chip has the capability of generating interrupts on the primaryPCI interrupt pins. This is done by setting a bit in the Outbound Doorbell Register within theMessaging Unit. Bits 28 through 31 correspond to PCI interrupts P_INTA# through P_INTD#respectively. Setting a bit within the register generates the corresponding PCI interrupt.Bits 27 through 0 in the Outbound Doorbell Register are all cleared in the default state. When anybit is set, a PCI interrupt is generated. The bit-field in the Address Translation Unit Interrupt PinRegister (ATUIPR) determines which PCI interrupt (P_INTA# through P_INTD#) is generated.Refer to PCI Local Bus Specification, Revision 2.2 for complete details on the bit-field definitionof the ATUIPR.2-8 Developer’s Manual