Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipTest FeaturesTable 14-4. Intel ® 80312 I/O Companion Chip Boundary Scan Register Bit Order (Sheet 13 of 13)# Cell Type NameFunctionSafe bit Control Signal Disable Value Disable Result"430 (CBSC_1, p_ad(46), bidir, X, 447, 0, Z)," &"431 (CBSC_1, p_ad(47), bidir, X, 447, 0, Z)," &"432 (CBSC_1, p_ad(44), bidir, X, 447, 0, Z)," &"433 (CBSC_1, p_ad(45), bidir, X, 447, 0, Z)," &"434 (CBSC_1, p_ad(43), bidir, X, 447, 0, Z)," &"435 (CBSC_1, p_ad(41), bidir, X, 447, 0, Z)," &"436 (CBSC_1, p_ad(42), bidir, X, 447, 0, Z)," &"437 (CBSC_1, p_ad(38), bidir, X, 447, 0, Z)," &"438 (CBSC_1, p_ad(37), bidir, X, 446, 0, Z)," &"439 (CBSC_1, p_ad(40), bidir, X, 446, 0, Z)," &"440 (CBSC_1, p_ad(34), bidir, X, 446, 0, Z)," &"441 (CBSC_1, p_ad(39), bidir, X, 446, 0, Z)," &"442 (CBSC_1, p_ad(35), bidir, X, 446, 0, Z)," &"443 (CBSC_1, p_ad(33), bidir, X, 446, 0, Z)," &"444 (CBSC_1, p_ad(32), bidir, X, 446, 0, Z)," &"445 (CBSC_1, p_ad(36), bidir, X, 446, 0, Z)," &"446 (BC_1, *, control, 0)," &"447 (BC_1, *, control, 0)," &"448 (BC_1, *, control, 0)," &"449 (BC_1, *, control, 0)," &"450 (BC_1, *, control, 0)," &"451 (BC_1, *, control, 0)," &"452 (BC_1, *, control, 0)," &"453 (BC_1, *, control, 0)," &"454 (BC_1, *, control, 0)," &"455 (BC_1, *, control, 0)" ;14-18 Developer’s Manual
Intel ® 80312 I/O Companion ChipTest Features14.1.5 TAP ControllerThe TAP (Test Access Port) controller is a 16-state synchronous finite state machine that controlsthe sequence of test logic operations. The TAP can be controlled via a bus master. The bus mastercan be either automatic test equipment or a component (i.e., PLD) that interfaces to the TAP. TheTAP controller changes state only in response to a rising edge of TCK. The value of the test modestate (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAPcontroller is initialized after power-up by applying a low to the TRST# pin. In addition, the TAPcontroller can be initialized by applying a high signal level on the TMS input for a minimum offive TCK periods. See Figure 14-2 for the state diagram of the TAP controller. An uninitializedTAP controller can result in erratic processor behavior even when there is no intention to use theJTAG portion of the processor.The behavior of the TAP controller and other test logic in each controller state is described in thefollowing subsections. For greater detail on the state machine and the public instructions, refer tothe IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (availablefrom the IEEE).Figure 14-2.TAP Controller State DiagramTRST# = 01Test - Logic -Reset00Run - Test /Idle1SELECT -DR - SCAN01SELECT -IR - SCAN011CAPTURE - DR1CAPTURE - IR0000SHIFT - DRSHIFT - IR11EXIT1 - DR1EXIT1 - IR10PAUSE- DR00PAUSE- IR0110EXIT2 - DR0EXIT2 - IR11UPDATE - DRUPDATE - IR1 0 10NOTE: All state transitions are based on the value of TMS.A6806-01Developer’s Manual 14-19
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Intel 80312 I/O Companion Chip - ECEE

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