Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.10.1.4 Master-AbortA Master-Abort is used when no target responds with a DEVSEL# within 5 clocks after theassertion of FRAME#. The Intel ® 80312 I/O companion chip bridge unit has two mechanisms forhandling Master-Aborts. The mechanism depends on the Master Abort Mode bit in the BridgeControl Register (BCR).When the Master Abort Mode bit is cleared, the bridge is operating in a PC compatibility mode.When a read transaction crosses the bridge in this mode and the target interface signals aMaster-Abort, the bridge returns all 1s (32-bits wide or 64-bits wide based on the size of theinitiating PCI bus) to the initiator during the repeated transaction and terminates normally (withTRDY#) on the initiating interface. When a write transaction crosses the bridge in this mode andthe target interface signals a Master-Abort, the bridge completes the transaction normally on theinitiating interface and discards the write data on the target interface. In both cases, the bridge setsthe Received Master Abort bit in the Primary Status Register (PSR) when the Master-Abortoccurred on the Primary interface and in the Secondary Status Register (SSR) when theMaster-Abort occurred on the Secondary interface.When the Master Abort Mode bit is set, the bridge signals a Master-Abort to the initiator of adelayed read or write transaction when that transaction causes a Master-Abort on the target bus.The bridge sets the corresponding Received Master Abort bit as in the previous case. When thetransaction that caused the Master-Abort on the target interface was a posted write transaction, thebridge asserts P_SERR# on the Primary interface (when enabled). The bridge terminates theposted write transaction on the initiating interface with a disconnect with or without data. TheReceived Master Abort bit is set in the appropriate status register corresponding to theMaster-Abort interface and the Signaled System Error bit in the PSR.A Master-Abort is not signaled during a Special Cycle transaction from either interface.4.10.2 Termination as a Slave (Target)4.10.2.1 RetryThe method for a target termination on either PCI interface is the assertion of the STOP# signal. APCI target asserts STOP# to request that the master terminate a transaction. The target will holdSTOP# asserted until the master deasserts FRAME#. IRDY# and TRDY# are independent oftarget termination so data may or may not be transferred. The only rule is that when STOP# isasserted when TRDY# is deasserted, the master will not wait for the final data transfer. Thefollowing sections summarize the bridge actions as a PCI target for termination situations. See thePCI Local Bus Specification, Revision 2.2 for details.Retry refers to a termination request to the initiator where data has not been transferred. The bridgeuses the Retry mechanism when the bridge:• is unable to provide resources for propagating the transaction to its destination.• accepts a delayed request.• receives a delayed request and it does not match any delayed completions held by the bridge.• is locked and the initiator does not own the LOCK# signal.A Retry is signaled when STOP# and DEVSEL# are asserted and TRDY# is deasserted on theinitiating interface.4-64 Developer’s Manual